公开(公告)号：US20180367141A1

公开(公告)日：2018-12-20

申请号：US16011518

申请日：2018-06-18

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  G11C5/06 ,  H03K19/0175 ,  G11C16/06 ,  G11C7/10 ,  G11C11/4063 ,  G11C5/14 ,  G11C11/413

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20180203759A1

公开(公告)日：2018-07-19

申请号：US15838161

申请日：2017-12-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US20180150420A1

公开(公告)日：2018-05-31

申请号：US15827825

申请日：2017-11-30

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ian Shaeffer

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/409 ,  G11C11/4076 ,  G06F3/06

CPC classification number: G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

公开(公告)号：US09870283B2

公开(公告)日：2018-01-16

申请号：US14864500

申请日：2015-09-24

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US20170372768A1

公开(公告)日：2017-12-28

申请号：US15616209

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G06F1/08 ,  G11C11/4096 ,  G11C11/408 ,  G06F1/32 ,  G11C11/4072 ,  G06F1/04 ,  G11C7/20 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US09824730B2

公开(公告)日：2017-11-21

申请号：US15228644

申请日：2016-08-04

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott C Best ,  Lei Luo ,  Ian Shaeffer

IPC: G06F12/00 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US09734921B2

公开(公告)日：2017-08-15

申请号：US14407318

申请日：2013-10-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ian Shaeffer

IPC: G11C29/44 ,  G11C29/00 ,  G06F11/10

CPC classification number: G11C29/4401 ,  G06F11/1016 ,  G06F11/1072 ,  G11C29/808 ,  G11C29/846

Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

公开(公告)号：US09705498B2

公开(公告)日：2017-07-11

申请号：US15187861

申请日：2016-06-21

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  H03K19/0175 ,  G11C7/00 ,  G11C7/10 ,  G11C5/06 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  G11C5/14

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20170186478A1

公开(公告)日：2017-06-29

申请号：US15389409

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G06F13/40 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US09632956B2

公开(公告)日：2017-04-25

申请号：US14874324

申请日：2015-10-02

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/02

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.