公开(公告)号：US20150162101A1

公开(公告)日：2015-06-11

申请号：US14407318

申请日：2013-10-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ian Shaeffer

IPC: G11C29/44 ,  G06F11/10

CPC classification number: G11C29/4401 ,  G06F11/1016 ,  G06F11/1072 ,  G11C29/808 ,  G11C29/846

Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

Abstract translation: 存储器设备（100）包括修复存储器块的额外列（114）。 这些修复存储器瓦片同时被以与主阵列的存储器瓦片相同的方式被访问。 修复列的输出代替主阵列（112）的列的输出。 取代的主阵列列由存储在外部的存储器件的标签（121）决定。 使用访问的部分地址查询外部标记。 如果访问的地址对应于外部标签中的地址，则将标签信息提供给存储设备。 标签信息确定主阵列中的哪个列由修复列的输出替代。 由于主阵列的每列在访问期间提供一位，所以修复列可以逐个单元替换主阵列单元。

公开(公告)号：US20150074437A1

公开(公告)日：2015-03-12

申请号：US14546687

申请日：2014-11-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/12 ,  G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract translation: 集成电路存储器控制器向存储器件输出处于第一状态的第一信号，以使存储器件内的同步数据发送和接收电路能够操作。 存储器控制器内的事务队列存储要被服务的存储器读和写请求，分别要求存储器件内的同步数据发送和接收电路的操作。 存储器控制器内的电源控制电路确定事务队列已经达到预定状态，并且作为响应，在第二状态下将第一信号输出到存储器件，以禁止存储器件内的同步数据发送和接收电路的操作。

公开(公告)号：US20140351673A1

公开(公告)日：2014-11-27

申请号：US14285467

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Brent Haukness ,  Scott C. Best ,  Wayne F. Ellis

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1092 ,  G06F2211/1092 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.

Abstract translation: 公开了一种存储器件，其包括用于存储数据字的存储位置行和备用行元件。 数据字通过用于产生用于校正X位错误的错误信息的错误代码进行编码，或者检测Y位错误，其中Y大于X.备用行元件具有替代的存储位置。 逻辑响应于检测到的错误，以（1）能够基于错误信息来校正数据字，其中存在不超过X位错误，以及（2）将备用行元素替换为存在行的一部分 数据字中至少有Y位错误。

公开(公告)号：US20140133536A1

公开(公告)日：2014-05-15

申请号：US14145966

申请日：2014-01-01

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/00

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract translation: 提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于 而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

公开(公告)号：US08717837B2

公开(公告)日：2014-05-06

申请号：US13899844

申请日：2013-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components.

Abstract translation: 具有存储器组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储器模块。 选通信号路径和数据信号路径被耦合到相应的存储器组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有存储器组件。 地址/控制信号路径沿着存储器组件延伸到终端结构，使得朝着终端结构传播的控制信号在对应于存储器组件的相对位置的逐渐更新的时间到达各个存储器组件的地址/控制输入。

公开(公告)号：US20140068172A1

公开(公告)日：2014-03-06

申请号：US13975873

申请日：2013-08-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali ,  Frederick A. Ware

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G06F12/08 ,  G06F12/1009 ,  Y02D10/13

Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

Abstract translation: 公开了一种刷新存储器的方法。 该方法包括从活动存储器访问活动存储器映射。 活动存储器映射由软件产生，并且识别与活动存储器相对应的地址和用于地址的相关联的刷新标准。 针对活动存储器的一部分评估刷新标准，并且基于刷新准则启动刷新活动存储器的一部分的操作。

公开(公告)号：US20140016423A1

公开(公告)日：2014-01-16

申请号：US13938130

申请日：2013-07-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。

公开(公告)号：US20130286706A1

公开(公告)日：2013-10-31

申请号：US13778534

申请日：2013-02-27

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G11C8/06 ,  G11C5/02

CPC classification number: G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

Abstract: Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.

Abstract translation: 描述了组织在物理存储体中的存储装置，并且包括可配置数据控制电路以支持多个数据宽度配置。 相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。 还描述了将配置值传递给可配置存储器设备并且支持多个宽度配置的点对点数据缓冲器的存储器控​​制器。

公开(公告)号：US20130262757A1

公开(公告)日：2013-10-03

申请号：US13890801

申请日：2013-05-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the address/control signal path and outputting the write data on the data signal path.

Abstract translation: 在由具有写定时校准模式的存储器组件填充的存储器模块中，经由地址/控制信号路径接收指定写入操作的控制信息，并经由数据信号路径接收与写操作对应的写数据。 每个存储器组件接收用于指示写入数据有效的定时信号的多个延迟版本，并且输出与定时信号的多个延迟版本对应的信号，以使得能够在存储器控制器中确定输出 对地址/控制信号路径进行控制信息，并在数据信号路径上输出写入数据。

公开(公告)号：US20250156350A1

公开(公告)日：2025-05-15

申请号：US18920424

申请日：2024-10-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.