公开(公告)号：US06768316B2

公开(公告)日：2004-07-27

申请号：US10316665

申请日：2002-12-11

Applicant: Yeo Kong Hoo ,  Christopher Vernon Smith

Inventor： Yeo Kong Hoo ,  Christopher Vernon Smith

IPC: G01N2700

CPC classification number: B32B15/08 ,  B32B15/14 ,  B32B15/20 ,  B32B27/308 ,  B32B2250/40 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2307/206 ,  B32B2457/08 ,  H01G2/20 ,  H05K1/0256 ,  H05K1/162 ,  H05K3/027 ,  H05K2201/0761 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2203/162 ,  Y10T29/49156 ,  Y10T428/24917

Abstract: A laminate comprising an insulation layer sandwiched between a pair of electrically conductive layers is prepared for electrical insulation testing by using a laser to remove a strip from at least one of the conductive layers proximate the edge of the laminate to electrically isolate a central, bulk portion of the conductive layer from the edges of the laminate. Conductive material that may be smeared across an edge of the laminate will not therefore provide an electrical short between the portion of the conductive layer surrounded by the slot and the second conductive layer on the opposite side of the insulation layer.

Abstract translation: 通过使用激光从邻近层压体的边缘的至少一个导电层去除条带来制备夹在一对导电层之间的绝缘层的层压板，用于电绝缘测试，以电绝缘中间部分 的导电层。 因此，可能被涂抹在层压体的边缘上的导电材料将不会在由狭缝围绕的导电层的部分与绝缘层的相对侧上的第二导电层之间提供电短路。

公开(公告)号：US20040069528A1

公开(公告)日：2004-04-15

申请号：US10267363

申请日：2002-10-09

Applicant: DOWA MINING CO., LTD.

Inventor： Masami Sakuraba ,  Masami Kimura ,  Takashi Ono ,  Noriyuki Ishii ,  Nobuyoshi Tukaguchi

IPC: H05K001/09

CPC classification number: H05K3/06 ,  C04B2237/125 ,  C04B2237/126 ,  C04B2237/127 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/407 ,  C04B2237/708 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/26 ,  H05K3/38 ,  H05K2201/0355 ,  H05K2201/0761 ,  H05K2203/0793 ,  H05K2203/0796 ,  H05K2203/121 ,  H01L2924/00

Abstract: A paste of brazing material of AgnullCunullTinullTiO2 system is printed to both sides of an AlN substrate; a copper sheet is then placed on both sides and heated in vacuum to be joined to the substrate. A resist having a desired-circuit pattern is coated on the surface of each copper sheet and etching is performed. A solution containing a mixture of EDTA, ammonia and aqueous hydrogen peroxide is then applied to dissolve away the unwanted brazing material and the like from between the circuit patterns without corroding the ceramic substrate and the metal sheet.

Abstract translation: 将Ag-Cu-Ti-TiO2系统的钎焊材料的糊料印刷到AlN衬底的两侧; 然后将铜片放置在两侧并在真空中加热以与基底接合。 具有所需电路图形的抗蚀剂涂覆在每个铜片的表面上，并进行蚀刻。 然后施加含有EDTA，氨和过氧化氢水溶液的溶液，从而在电路图案之间消除不想要的钎焊材料等，而不会腐蚀陶瓷基底和金属片。

公开(公告)号：US20040022934A1

公开(公告)日：2004-02-05

申请号：US10408422

申请日：2003-04-07

Applicant: Shipley Company, L.L.C.

Inventor： Mei Kiu Leung ,  Willetta Lai ,  Pit Kai Peter Cheng ,  Cecilia Po Sze Wong

IPC: B05D005/12 ,  B05D003/04 ,  B05D003/10

CPC classification number: H05K3/244 ,  H05K3/26 ,  H05K3/383 ,  H05K2201/0761 ,  H05K2201/09063 ,  H05K2203/121

Abstract: A process and composition for manufacturing printed wiring boards that reduces or eliminates the problem of depositing electroless nickel in through holes that are not designed to be metal plated is provided. Also provided by the present invention is a method and composition for depositing a final finish that is even and bright. The present invention is particularly suitable for the manufacture of printed circuit boards containing one or more electroless nickel-immersion gold layers.

Abstract translation: 提供一种用于制造印刷线路板的方法和组合物，其减少或消除了将非电解镍沉积在未设计为金属镀覆的通孔中的问题。 本发明还提供了一种沉积最终光洁度的方法和组合物，其是均匀且明亮的。 本发明特别适用于制造含有一种或多种无电镀镍浸镀金层的印刷电路板。

公开(公告)号：US20030226687A1

公开(公告)日：2003-12-11

申请号：US10456562

申请日：2003-06-09

Inventor： Tatsuo Kataoka ,  Tatsuya Aoki ,  Yasunori Matsumura

IPC: H05K001/00 ,  H05K001/09 ,  G03F007/20 ,  G03F007/40

CPC classification number: H05K3/26 ,  G03F7/40 ,  H05K3/067 ,  H05K3/384 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/0761 ,  H05K2203/0307 ,  H05K2203/0789 ,  H05K2203/1476

Abstract: Provided is a method of manufacturing a printed wiring board which keeps a good etching factor of formed circuits, eliminates an etching residue and can effectively prevent the occurrence of surface layer migration. In the method of manufacturing a printed wiring board which involves using a copper-clad laminate, which is fabricated by bonding together a conductive-circuit formation layer obtained by laminating a copper layer and a dissimilar metal layer other than copper, and an insulating base material so that the copper layer of the conductive-circuit formation layer is exposed to the surface, the above etching of the conductive-circuit formation layer includes a primary etching step of simultaneously dissolving the copper layer and the dissimilar metal layer other than copper which form the conductive-circuit formation layer and a secondary etching step which involves using, after the completion of the primary etching step, a selective etching solution to dissolve only metals which constitute the dissimilar metal layer without dissolving copper.

Abstract translation: 提供一种制造印刷电路板的方法，其保持形成的电路的良好蚀刻因子，消除蚀刻残留物并且可以有效地防止表面层迁移的发生。 在制造印刷电路板的方法中，涉及使用通过将通过层叠铜层而获得的导电电路形成层与铜以外的不同金属层接合的导电电路形成层而制造的覆铜层压板和绝缘基材 使得导电电路形成层的铜层暴露于表面，导电电路形成层的上述蚀刻包括一次蚀刻步骤，同时溶解形成铜箔的铜层和除了铜之外的不同金属层 导电电路形成层和二次蚀刻步骤，其包括在完成一次蚀刻步骤之后使用选择性蚀刻溶液，以仅溶解构成异种金属层的金属而不溶解铜。

公开(公告)号：US06207595B1

公开(公告)日：2001-03-27

申请号：US09033505

申请日：1998-03-02

Applicant: Bernd K. Appelt ,  Lawrence R. Blumberg ,  William T. Fotorny ,  Ross D. Havens ,  Robert M. Japp ,  Kostas Papathomas ,  Jan Obrzut ,  Mark D. Poliks ,  Amarjit S. Rai

Inventor： Bernd K. Appelt ,  Lawrence R. Blumberg ,  William T. Fotorny ,  Ross D. Havens ,  Robert M. Japp ,  Kostas Papathomas ,  Jan Obrzut ,  Mark D. Poliks ,  Amarjit S. Rai

IPC: B32B2704

CPC classification number: H01L23/564 ,  H01L23/08 ,  H01L23/145 ,  H01L2924/0002 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/0761 ,  Y10T442/2475 ,  Y10T442/2959 ,  Y10T442/2992 ,  H01L2924/00

Abstract: A fabric material and method of its manufacture suitable for use in electronic packages including chip carriers. High insulation resistance is exhibited when subjected to high temperatures and humidity stress conditions.

Abstract translation: 一种其制造的织物材料及其制造方法，其适用于包括芯片载体的电子封装。 当受到高温和高湿度条件的影响时，表现出高的绝缘电阻。

公开(公告)号：US5589446A

公开(公告)日：1996-12-31

申请号：US477116

申请日：1995-06-07

Applicant: Greg R. Unruh

Inventor： Greg R. Unruh

IPC: C11D7/24 ,  C11D7/26 ,  C11D7/28 ,  C11D7/32 ,  C11D7/34 ,  C11D7/50 ,  C23G5/02 ,  H05K3/26 ,  C07D323/00

CPC classification number: C11D7/262 ,  C11D7/261 ,  C11D7/5004 ,  C23G5/02 ,  H05K3/26 ,  C11D7/24 ,  C11D7/267 ,  C11D7/28 ,  C11D7/32 ,  C11D7/34 ,  H05K2201/0761 ,  H05K2203/121

Abstract: A composition and method for the removal of ionic salt deposits from a surface using an organic solvent of low polarity and a complexing agent. The complexing agent is chosen from a group which includes podands, cryptands, and coronands. The method provides nearly complete removal of ionic salt deposits with a single washing of the surface with the low polar cleaning mixture.

Abstract translation: 使用低极性的有机溶剂和络合剂从表面除去离子盐沉积物的组合物和方法。 络合剂选自包括podands，cryptands和coronand的组。 该方法通过用低极性清洗混合物对表面进行单次洗涤，几乎完全除去离子盐沉积物。

公开(公告)号：US5380560A

公开(公告)日：1995-01-10

申请号：US921186

申请日：1992-07-28

Applicant: Suryanarayana Kaja ,  Shyama P. Mukherjee ,  Eugene J. O'Sullivan ,  Milan Paunovic

Inventor： Suryanarayana Kaja ,  Shyama P. Mukherjee ,  Eugene J. O'Sullivan ,  Milan Paunovic

IPC: C23C18/16 ,  C23C18/30 ,  H05K3/24 ,  C23C26/00

CPC classification number: H05K3/465 ,  C23C18/1607 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1635 ,  C23C18/1637 ,  C23C18/30 ,  C23C18/32 ,  H05K3/244 ,  H05K2201/0154 ,  H05K2201/0761 ,  H05K2203/0716 ,  H05K2203/072 ,  H05K2203/0766 ,  H05K3/384 ,  H05K3/388

Abstract: A method of selectively seeding or activating metal interconnections patterned on polyimide dielectric surfaces using an aqueous solution of palladium sulfate, palladium perchlorate, palladium trifluoromethane sulfonate, palladium nitrate or other palladium salts having poorly coordinating counter ions. This strongly selective seeding and the corresponding ability to reliably remove all traces of the seeding material from the polyimide surface eliminates shorting, bridging and reduction of breakdown voltage during electroless plating of a thin layer of nickel or cobalt.

Abstract translation: 使用硫酸钯，高氯酸钯，三氟甲烷磺酸钯，硝酸钯或具有配位不良的抗衡离子的其它钯盐的水溶液选择性地接种或活化在聚酰亚胺电介质表面上形成的金属互连的方法。 这种强选择性接种和相应的能够从聚酰亚胺表面可靠地除去接种材料的痕迹消除了在镍或钴的薄层的化学镀期间短路，桥接和降低击穿电压。

公开(公告)号：US5354415A

公开(公告)日：1994-10-11

申请号：US584

申请日：1993-01-04

Applicant: Yasuhito Fushii ,  Miyuki Nakamura ,  Yukihiko Nakajima ,  Kazuo Kato ,  Akira Miyai ,  Kazuyuki Hiruta

Inventor： Yasuhito Fushii ,  Miyuki Nakamura ,  Yukihiko Nakajima ,  Kazuo Kato ,  Akira Miyai ,  Kazuyuki Hiruta

IPC: H05K1/03 ,  H05K3/06 ,  H05K3/26 ,  H05K3/38 ,  C23F1/00

CPC classification number: H05K3/06 ,  C04B37/026 ,  H05K3/26 ,  H05K3/38 ,  C04B2235/6565 ,  C04B2235/6581 ,  C04B2235/96 ,  C04B2237/12 ,  C04B2237/121 ,  C04B2237/122 ,  C04B2237/124 ,  C04B2237/125 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/407 ,  C04B2237/52 ,  C04B2237/525 ,  C04B2237/704 ,  C04B2237/706 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0355 ,  H05K2201/0761 ,  H05K2203/0789

Abstract: Method for forming a ceramic circuit board by forming a metal circuit pattern on a ceramic board through an active metal ingredient-containing brazing material and removing an unnecessary part of the brazing material by chemical liquor treatment.

Abstract translation: 通过在陶瓷板上形成金属电路图形并通过含有活性金属成分的钎焊材料形成陶瓷电路板并通过化学液体处理除去不需要的部分钎焊材料的方法。

公开(公告)号：US5167992A

公开(公告)日：1992-12-01

申请号：US667778

申请日：1991-03-11

Applicant: Charles W. C. Lin ,  Ian Y. K. Yee

Inventor： Charles W. C. Lin ,  Ian Y. K. Yee

IPC: C23C18/16 ,  H05K3/24

CPC classification number: H05K3/244 ,  C23C18/1608 ,  C23C18/1635 ,  C23C18/1889 ,  C23C18/2006 ,  C23C18/208 ,  C23C18/32 ,  C23C18/42 ,  H05K2201/0347 ,  H05K2201/0761 ,  H05K2203/0392 ,  H05K2203/095

Abstract: A method for electrolessly plating an overcoat metal on a metal conductor disposed on a dielectric surface of a substrate. The method includes removing carbonized film from the dielectric surface by applying a plasma discharge, acid treating the metal conductor by dipping the substrate in a first acid solution in order to clean the surface of the metal conductor, activating the metal conductor to allow electroless plating thereon by dipping the substrate in a metal activator solution, deactivating the dielectric surface to prevent electroless plating thereon without deactivating the metal conductor by dipping the substrate in a second acid solution, and plating an overcoat metal on the metal conductor by dipping the substrate in an electroless plating solution so that the overcoat metal plates on and coats the metal conductor without plating on the dielectric surface.

Abstract translation: 在设置在基板的电介质表面上的金属导体上无电镀电镀金属的方法。 该方法包括通过施加等离子体放电来从电介质表面去除碳化膜，通过将基底浸渍在第一酸溶液中来酸化处理金属导体，以清洁金属导体的表面，激活金属导体以允许金属导体在其上进行无电镀 通过将基底浸渍在金属活化剂溶液中，使电介质表面失活以防止其上化学镀，而不使金属导体通过将基底浸渍在第二酸溶液中而使金属导体失活，并且通过将基底浸渍在无电镀中而在金属导体上镀覆外涂层金属 电镀溶液，使得外涂金属板在金属导体上涂覆并涂覆在电介质表面上。

公开(公告)号：US4824693A

公开(公告)日：1989-04-25

申请号：US157933

申请日：1988-02-19

Applicant: Michael Schlipf ,  Rolf Zondler

Inventor： Michael Schlipf ,  Rolf Zondler

IPC: B23K1/20 ,  C23C18/18 ,  G02F1/1343 ,  G02F1/1345 ,  G09F9/00 ,  H01R43/16 ,  H05K3/24 ,  B05D5/12

CPC classification number: H05K3/24 ,  G02F1/1345 ,  H05K2201/0326 ,  H05K2201/0347 ,  H05K2201/0761

Abstract: To deposit a solderable metal layer on conductive paths (4) of ITO on substrates of display devices (1) by an electroless method, the conductive paths are activated, prior to the deposition, and the areas not covered by the conductive paths are subsequently inactivated. The activated paths are then metallized with a solderable metal layer so that integrated circuits can be soldered to the metallized conductive paths.

Abstract translation: 为了通过无电镀方法将可焊接的金属层沉积在ITO的导电路径（4）上，在沉积之前，导电路径被激活，并且未被导电路径覆盖的区域随后被钝化 。 激活的路径然后用可焊接金属层进行金属化，使得集成电路可以焊接到金属化导电路径。