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公开(公告)号：US20080042296A1
公开(公告)日：2008-02-21
申请号：US11858905
申请日：2007-09-21
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 钝化层沉积在电介质层上，在钝化层的表面上形成厚的第二层电介质。 在厚的第二层电介质中产生厚而宽的互连线。 也可以消除第一层电介质，在已经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。
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公开(公告)号：US20080042294A1
公开(公告)日：2008-02-21
申请号：US11856076
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20080042293A1
公开(公告)日：2008-02-21
申请号：US11856074
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/58
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20080042285A1
公开(公告)日：2008-02-21
申请号：US11856073
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20080042280A1
公开(公告)日：2008-02-21
申请号：US11769736
申请日：2007-06-28
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L23/5227 , H01L23/53238 , H01L23/53252 , H01L24/05 , H01L24/06 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/94 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05084 , H01L2224/05553 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/1147 , H01L2224/1308 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13171 , H01L2224/13173 , H01L2224/13176 , H01L2224/13181 , H01L2224/13183 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48747 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/73204 , H01L2224/838 , H01L2224/85201 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12044 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/30105 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01032 , H01L2924/01031 , H01L2224/48869 , H01L2224/48744 , H01L2224/05552
摘要： A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.
摘要翻译： 半导体芯片结构包括半导体衬底，电路结构，钝化层，第一粘附/阻挡层，金属帽和金属层。 半导体衬底具有位于衬底表面的表面层上的多个电子器件。 电路结构具有彼此电连接并与电气装置电连接的多个电路层。 其中一个电路层具有多个焊盘。 钝化层位于电路结构上，具有贯穿钝化层的多个开口。 开口露出垫。 第一粘附/阻挡层在焊盘和钝化层之上。 金属盖位于第一粘附/阻挡层和钝化层上。 金属层在金属层上。
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公开(公告)号：US20080003807A1
公开(公告)日：2008-01-03
申请号：US11858904
申请日：2007-09-21
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20080003806A1
公开(公告)日：2008-01-03
申请号：US11856082
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20080001302A1
公开(公告)日：2008-01-03
申请号：US11856078
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20080001293A1
公开(公告)日：2008-01-03
申请号：US11856072
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/538
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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公开(公告)号：US20070275503A1
公开(公告)日：2007-11-29
申请号：US11750332
申请日：2007-05-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
CPC分类号： H01L24/05 , C25D3/48 , C25D5/022 , H01L24/03 , H01L24/11 , H01L24/12 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/02166 , H01L2224/0231 , H01L2224/03 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05024 , H01L2224/05082 , H01L2224/05144 , H01L2224/05166 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/05569 , H01L2224/05644 , H01L2224/0603 , H01L2224/1147 , H01L2224/13021 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/29298 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48463 , H01L2224/48644 , H01L2224/48699 , H01L2224/48844 , H01L2224/838 , H01L2224/85 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2924/01013 , H01L2224/48744 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552
摘要： The present invention provides a method for fabricating chip package comprises the following steps: forming a photoresist layer on a metal layer over a passivation layer, an opening in the photoresist layer exposing the metal layer, wherein said forming the photoresist layer comprises exposing the photoresist layer using 1X stepper with at least two of G-line, H-line and I-line; electroplating a gold layer over the metal layer exposed by the opening with an electroplating solution containing gold and sulfite ion; removing the photoresist layer and the metal layer not under the gold layer.
摘要翻译： 本发明提供了一种用于制造芯片封装的方法，包括以下步骤：在钝化层上的金属层上形成光致抗蚀剂层，在光致抗蚀剂层中形成露出金属层的开口，其中所述形成光致抗蚀剂层包括使光致抗蚀剂层 使用1路步进与G线，H线和I线至少两个; 在含有金和亚硫酸根离子的电镀溶液中，通过开口电镀金层上金属层; 去除不在金层下面的光致抗蚀剂层和金属层。
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