公开(公告)号：US20250007693A1

公开(公告)日：2025-01-02

申请号：US18217445

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Santosh GHOSH ,  Qian WANG ,  Manoj R. SASTRY

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: Kyber is a secure key encapsulation mechanism (KEM) for secure key exchange. Performance overhead associated with use of Kyber for secure key exchange is reduced by computing multiple coefficients of different polynomials for independent operations in parallel and localizing them in memory for fast access for polynomial multiplications used in key generation, encapsulation, and decapsulation allowing for parallelization of Keccak calls.

公开(公告)号：US20250007600A1

公开(公告)日：2025-01-02

申请号：US18344191

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Yang-Seok Choi ,  Sagar Dhakal ,  Husam Elfadil ,  Thushara Hewavithana ,  Xiaofeng Li ,  Peng Lu ,  Tariq Qureshi ,  Jan Schreck

IPC: H04B7/08 ,  H04B7/0426 ,  H04B7/06

Abstract: Techniques are disclosed to address issues related to the computation of channel state information (CSI) and angular spectrum (AS) to perform beamforming. The CSI and AS, as well as various statistical channel parameters of a wireless channel, may be computed using different techniques, which include the use of domain knowledge enhanced neural networks (DKE-NNs). The CSI and AS may be further utilized to perform beamforming using various techniques. One of these techniques may include the implementation of eigen beamforming, which provides artificially generated power at locations within the AS that are identified with estimated eigenvector beam locations. As a result of the artificially-generated power, the resulting vector decomposition used to provide the beamforming weights results in widened eigenvector beams.

公开(公告)号：US20250007278A1

公开(公告)日：2025-01-02

申请号：US18216447

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Krzysztof Domanski ,  Robert Haeussler ,  Harshit Dhakad

IPC: H02H9/02

Abstract: An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. First and second circuitry are coupled with the conductive contact. First and second supply lines are coupled with and provide power to the first circuitry, the first supply line providing a first voltage, and the second supply line providing a second voltage. The second circuitry is further coupled with the second supply line and a third supply line. The third supply line is to provide a third voltage and may provide a path for a current associated with an electrostatic discharge (ESD) event. A resistive element is coupled between the first supply line and the third supply line. The resistive element may reduce a current in the first supply line associated with an ESD event.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20250006791A1

公开(公告)日：2025-01-02

申请号：US18346227

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dominique A. Adams ,  Gauri Auluck ,  Pratyush P. Buragohain ,  Scott B. Clendenning ,  Punyashloka Debashis ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

公开(公告)号：US20250006790A1

公开(公告)日：2025-01-02

申请号：US18345931

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Shishir Pandya ,  James Kally ,  Robert Ehlert ,  Tahir Ghani

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/167 ,  H01L29/45

Abstract: In some implementations, a device may include a channel material. In addition, the device may include a contact metal. The device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. Moreover, the device may include a second layer between the contact metal and the first layer, the second layer having phosphorus and silicon.

公开(公告)号：US20250006652A1

公开(公告)日：2025-01-02

申请号：US18346098

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Francisco Maya ,  Bhaskar Jyoti Krishnatreya ,  Tan Nguyen ,  Siyan Dong ,  Alveera Gill ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

公开(公告)号：US20250006645A1

公开(公告)日：2025-01-02

申请号：US18343892

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xiao Liu ,  Bohan Shan ,  Dingying Xu ,  Gang Duan ,  Haobo Chen ,  Hongxia Feng ,  Jung Kyu Han ,  Xiaoying Guo ,  Zhixin Xie ,  Xiyu Hu ,  Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Changhua Liu ,  Yosuke Kanaoka

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/58 ,  H01L25/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20250006623A1

公开(公告)日：2025-01-02

申请号：US18217056

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Shuqi Lai ,  Jieying Kong ,  Dilan Seneviratne ,  Whitney Bryks

IPC: H01L23/498

Abstract: Microelectronic integrated circuit package structures include one or more integrated circuit (IC) package metallization levels comprising metallization features. A dielectric material is adjacent to one or more of the metallization features, where the dielectric material comprises a matrix material and a surfactant. A plurality of substantially spherical pores are within the matrix material, where the substantially spherical pores are surrounded by an outer shell comprising the matrix material.