公开(公告)号：US20180048019A1

公开(公告)日：2018-02-15

申请号：US15790529

申请日：2017-10-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Severin Larfaillou ,  Delphine Guy-Bouyssou

IPC: H01M10/052 ,  H01M4/1395 ,  H01M4/134 ,  H01M4/04 ,  H02J7/00 ,  H01M4/38 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44 ,  H01M4/40

CPC classification number: H01M10/052 ,  H01M4/0445 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/38 ,  H01M4/382 ,  H01M4/405 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44 ,  H02J7/007

Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.

公开(公告)号：US20180026249A1

公开(公告)日：2018-01-25

申请号：US15440683

申请日：2017-02-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed Boufnichel ,  Julien Ladroue

IPC: H01M2/20

Abstract: Identical planar electronic components are stacked in an assembly. Each component has two contact metallizations positioned on edges of a same surface of the component. The components are stacked along a common axis. Each successive component is rotated about the common axis by a fixed angle. A value of the fixed angle is selected to position, side by side, the contact metallization of one component and the contact metallization of another next component adjacent to each other in the stack. Electrical connections are provided between two adjacent contact metallizations.

公开(公告)号：US20180026027A1

公开(公告)日：2018-01-25

申请号：US15436998

申请日：2017-02-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/36 ,  H01L29/167 ,  H01L27/08 ,  H01L21/265 ,  H01L21/324 ,  H02H9/04 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/0814 ,  H01L29/0684 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66113 ,  H01L29/861 ,  H02H9/044

Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.

公开(公告)号：US20170287892A1

公开(公告)日：2017-10-05

申请号：US15243552

申请日：2016-08-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L27/02 ,  H01L29/747 ,  H01L29/87 ,  H01L29/74

CPC classification number: H01L29/747 ,  H01L27/0248 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/7404 ,  H01L29/7416 ,  H01L29/87

Abstract: A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

公开(公告)号：US09780366B2

公开(公告)日：2017-10-03

申请号：US14470827

申请日：2014-08-27

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed Boufnichel ,  Jean-Christophe Houdbert

IPC: H01M4/38 ,  H01L31/0236 ,  H01M4/04 ,  H01M4/134 ,  H01M4/1395 ,  C09K13/00 ,  H01L21/3065 ,  H01M4/02

CPC classification number: H01M4/386 ,  C09K13/00 ,  H01L21/3065 ,  H01L31/0236 ,  H01L31/02363 ,  H01M4/049 ,  H01M4/134 ,  H01M4/1395 ,  H01M2004/021 ,  H01M2004/027

Abstract: A method for forming a rough silicon wafer including the successive steps of: performing a plasma etching of a surface of the wafer in conditions suitable to obtain a rough structure, and performing two successive ion milling steps, one at an incidence in the range of 0 to 10°, the other at an incidence in the range of 40 to 60° relative to the normal to the wafer.

公开(公告)号：US09755541B2

公开(公告)日：2017-09-05

申请号：US14956482

申请日：2015-12-02

Applicant: STMicroelectronics (Tours) SAS

Inventor： Laurent Gonthier ,  Muriel Nina ,  Romain Pichon

IPC: H02M7/162 ,  H02M1/08 ,  H02M7/06 ,  H02M7/12

CPC classification number: H02M7/162 ,  H02M1/081 ,  H02M7/062 ,  H02M7/125 ,  H02M7/1623

Abstract: An AC/DC converter includes: a first terminal and a second terminal for receiving an AC voltage and a third terminal and a fourth terminal for supplying a DC voltage. A rectifying bridge includes input terminals respectively coupled to the first terminal and the second terminal, and output terminals respectively coupled to the third terminal and fourth terminal. A first branch of the rectifying bridge includes, connected between the output terminals, two series-connected thyristors with a junction point of the two thyristors being connected to a first one of the input terminals. A second branch of the rectifying bridge is formed by series connected diodes. A control circuit is configured to generate control signals for application to the control gates of the thyristors.

公开(公告)号：US09722061B2

公开(公告)日：2017-08-01

申请号：US14731563

申请日：2015-06-05

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Dalaf Ali

IPC: H01L29/66 ,  H01L29/747 ,  H01L29/06

CPC classification number: H01L29/747 ,  H01L29/0638

Abstract: A bidirectional switch is formed in a semiconductor substrate of a first conductivity type. The switch includes first and second thyristors connected in antiparallel extending vertically between front and rear surfaces of the substrate. A vertical peripheral wall of the second conductivity type connects the front surface to the rear surface and surrounds the thyristors. On the front surface, in a ring-shaped region of the substrate separating the vertical peripheral wall from the thyristors, a first region of the first conductivity type is provided having a doping level greater than the substrate and having the shape of a ring-shaped band portion partially surrounding the first thyristor and stopping at the level of the adjacent region between the first and second thyristors.

公开(公告)号：US09685778B2

公开(公告)日：2017-06-20

申请号：US14725342

申请日：2015-05-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu Rouviere ,  Laurent Moindron ,  Christian Ballon

IPC: H02H3/20 ,  H01L29/732 ,  H01L27/07 ,  H01L29/87 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872

CPC classification number: H02H3/20 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0629 ,  H01L27/0761 ,  H01L28/20 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7827 ,  H01L29/87 ,  H01L29/872

Abstract: An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.

公开(公告)号：US09680468B2

公开(公告)日：2017-06-13

申请号：US14957984

申请日：2015-12-03

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick Hague ,  Samuel Menard

IPC: H03K17/72 ,  H03K17/735 ,  H01L29/74 ,  H01L29/747 ,  H03K17/725 ,  H03K17/06 ,  H03K17/16 ,  H03K17/74

CPC classification number: H03K17/735 ,  H01L29/7408 ,  H01L29/7412 ,  H01L29/747 ,  H03K17/06 ,  H03K17/16 ,  H03K17/725 ,  H03K17/74 ,  H03K2017/066

Abstract: A bidirectional power switch includes first and second thyristors connected in antiparallel between first and second conduction terminals of the switch. The first thyristor is of an anode-gate thyristor, and the second thyristor is of a cathode-gate thyristor. The gates of the first and second thyristors are coupled to a same control terminal of the switch by respective dipole circuits. At least one of the dipole circuits is formed by at least one diode or at least one resistor.

公开(公告)号：US20170019526A1

公开(公告)日：2017-01-19

申请号：US15045935

申请日：2016-02-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Jean-Michel Simonnet ,  Christian Ballon

IPC: H04M1/74 ,  H04M19/08 ,  H04M3/00 ,  H02H9/04

CPC classification number: H04M1/745 ,  H01L27/0248 ,  H01L27/0262 ,  H01L29/0638 ,  H01L29/74 ,  H02H9/041 ,  H02H9/043 ,  H04M3/005 ,  H04M3/18 ,  H04M19/08 ,  H04M2201/80

Abstract: A structure protects a SLIC telephone line interface against overvoltages lower than a negative threshold or higher than a positive threshold. The structure includes at least one thyristor connected between each conductor of the telephone line and a reference potential. For all of the included thyristors, a metallization corresponding to the main electrode on the gate side is in contact, by its entire surface, with a corresponding semiconductor region. Furthermore, the gate of each thyristor is directly connected to a voltage source defining one of the thresholds.

Abstract translation: 结构保护SLIC电话线接口免于低于负阈值或高于正阈值的过电压。 该结构包括连接在电话线的每个导体和参考电位之间的至少一个晶闸管。 对于所有包括的晶闸管，对应于栅极侧的主电极的金属化通过其整个表面与相应的半导体区域接触。 此外，每个晶闸管的栅极直接连接到限定其中一个阈值的电压源。