公开(公告)号：US09536836B2

公开(公告)日：2017-01-03

申请号：US15167306

申请日：2016-05-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material.

Abstract translation: MIS接触结构包括半导体材料层，具有形成在其中的接触开口的绝缘材料层，具有基本上垂直取向的部分和基本上水平取向的部分的接触绝缘材料层，接触层的垂直取向部分 绝缘材料接触接触开口的侧壁的部分而不是全部接触半导体层的接触绝缘材料层的水平取向部分。 导电材料位于接触开口内的接触绝缘材料层上，导电材料层具有垂直取向的部分和水平取向的部分，以及定位在接触开口中的导电触点，其接触导电材料层的最上表面， 接触层绝缘材料。

公开(公告)号：US09530843B2

公开(公告)日：2016-12-27

申请号：US14738336

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

Abstract translation: 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层 的多层应变通道部分。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。

公开(公告)号：US20160372576A1

公开(公告)日：2016-12-22

申请号：US15255628

申请日：2016-09-02

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract translation: 本发明的实施例可以包括将嵌入的蚀刻阻挡层结合到具有替换金属栅极的场效应晶体管（FET）的替换金属栅极层以及由此形成的结构的方法。 嵌入的蚀刻停止层可以由嵌入的掺杂剂原子组成，并且可以使用离子注入形成。 嵌入的蚀刻停止层可以使得替换金属栅极层的移除更容易和更可控，从而提供水平表面和确定的深度以用作栅极盖形成的基底。 栅极帽可以将栅极与相邻的自对准电触头绝缘。

公开(公告)号：US09478658B2

公开(公告)日：2016-10-25

申请号：US14717551

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L29/7841 ,  H01L29/785

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

公开(公告)号：US09472470B2

公开(公告)日：2016-10-18

申请号：US14564323

申请日：2014-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.

Abstract translation: 一种方法，包括在由半导体衬底制成的半导体鳍片的相对侧壁上形成翅片间隔物，形成与翅片间隔件直接接触的电介质层，使得翅片的顶表面和翅片间隔件的顶表面保持暴露，凹陷 翅片间隔件的一部分，去除翅片间隔件以形成开口，并且在开口中外延生长未熔化的源极漏极区域，其中未熔化的源极漏极区域的横向生长通过电介质层约束在相对的两侧。

公开(公告)号：US09455330B2

公开(公告)日：2016-09-27

申请号：US14550019

申请日：2014-11-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L21/44 ,  H01L29/66 ,  H01L21/283 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract translation: 本发明的实施例可以包括将嵌入的蚀刻阻挡层结合到具有替换金属栅极的场效应晶体管（FET）的替换金属栅极层以及由此形成的结构的方法。 嵌入的蚀刻停止层可以由嵌入的掺杂剂原子组成，并且可以使用离子注入形成。 嵌入的蚀刻停止层可以使得替换金属栅极层的移除更容易和更可控，从而提供水平表面和确定的深度以用作栅极盖形成的基底。 栅极帽可以将栅极与相邻的自对准电触头绝缘。

公开(公告)号：US09455141B2

公开(公告)日：2016-09-27

申请号：US14574533

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kanggou Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02587 ,  H01L21/02612 ,  H01L21/02664 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/66795

Abstract: Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon layer on top of a BOX. At least one fin upon a thin layer of silicon and a hard mask layer over the at least one fin is formed using the silicon layer on top of the BOX. A SiGe layer is epitaxially grown from exposed portions of the fin and the thin layer of silicon. Spacers are formed on sidewalls of the hard mask. Regions of the SiGe layer and the thin layer of silicon not protected by the spacers are etched, such that portions of the BOX are exposed. A condensation process converts the fin to SiGe and to convert the SiGe layer to oxide. The hard mask, the spacers, and the oxide layer are removed.

Abstract translation: 本发明的实施例包括制造SiGe鳍片的方法和所得到的结构。 提供SOI衬底，其至少包括在BOX顶部的硅层。 使用BOX顶部的硅层，在至少一个散热片上的薄层硅层和硬掩模层上形成至少一个鳍片。 SiGe层从翅片和薄层硅的暴露部分外延生长。 垫片形成在硬掩模的侧壁上。 SiGe层的区域和未被间隔物保护的硅的薄层被蚀刻，使得BOX的部分被暴露。 冷凝过程将翅片转换成SiGe并将SiGe层转化为氧化物。 去除硬掩模，间隔物和氧化物层。

公开(公告)号：US09443948B2

公开(公告)日：2016-09-13

申请号：US14532122

申请日：2014-11-04

Applicant: GlobalFoundries Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/775 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US20160225766A1

公开(公告)日：2016-08-04

申请号：US15096681

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan Veera Venkata Satya Surisetty

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41766 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

公开(公告)号：US20160181105A1

公开(公告)日：2016-06-23

申请号：US14572975

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/225 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161

Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Abstract translation: 通过以下步骤构造SiGe翅片：（i）提供包括从基底层向上方延伸的含硅基底层和含硅的第一翅片结构的中间子组件; （ii）通过用包括硅的预热氧化层覆盖基层的顶表面的至少一部分和第一鳍结构的第一和第二侧表面的至少一部分来精炼子组件 锗（SiGe）; 和（iii）通过热氧化预热氧化层以使Ge含量从预热氧化层迁移到基层的至少一部分和第一翅片结构的至少一部分中，进一步细化子组件。