公开(公告)号：US20070074389A1

公开(公告)日：2007-04-05

申请号：US11588682

申请日：2006-10-27

Applicant: Damion Searls ,  Edward Osburn

Inventor： Damion Searls ,  Edward Osburn

IPC: H05K3/30

CPC classification number: H01L23/49844 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1531 ,  H01L2924/19106 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/1006 ,  H05K2201/10166 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  Y10T29/4913 ,  Y10T29/49147 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract translation: 在一个实施例中，本发明包括将半导体器件安装到电路板的第一侧的方法; 以及将至少一个电压调节器装置安装到所述电路板的第二侧，所述第二侧与所述第一侧相对。 电压调节器装置可以是输出滤波器，电感器，电容器等。 在某些实施例中，器件可以位于半导体器件的正下方。

公开(公告)号：US20070045868A1

公开(公告)日：2007-03-01

申请号：US11552256

申请日：2006-10-24

Applicant: HIDETO FURUYAMA ,  Hiroshi Hamasaki

Inventor： HIDETO FURUYAMA ,  Hiroshi Hamasaki

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0268 ,  H05K1/141 ,  H05K7/023 ,  H05K2201/049 ,  H05K2201/10704 ,  H05K2201/10719 ,  H01L2924/00

Abstract: A LSI package encompasses: an interposer having board-connecting joints, which facilitate connection with a printed wiring board, and module-connecting terminals, part of the module-connecting terminals are assigned as interposer-site monitoring terminals; a signal processing LSI mounted on the interposer; and an I/F module having a plurality of interposer-connecting terminals, which are arranged to correspond to arrangement of the module-connecting terminals, and a transmission line to establish an external interconnection of signal, which is transmitted from the signal processing LSI, part of the interposer-connecting terminals are assigned as module-site monitoring terminals. The interposer-site and module-site monitoring terminals are configured to flow a monitoring current to confirm electric contact between the signal processing LSI and the I/F module.

Abstract translation: LSI封装包括：具有板连接接头的插入件，其便于与印刷线路板的连接，以及模块连接端子，部分模块连接端子被分配为插入器位置监视端子; 安装在所述插入器上的信号处理LSI; 以及具有多个插入器连接端子的I / F模块，其被配置为对应于模块连接端子的配置，以及传输线，用于建立从信号处理LSI发送的信号的外部互连， 插入器连接端子的一部分被分配为模块站点监视终端。 中介站点和模块现场监视终端被配置为流动监视电流以确认信号处理LSI和I / F模块之间的电接触。

公开(公告)号：US20060291180A1

公开(公告)日：2006-12-28

申请号：US11165631

申请日：2005-06-23

Applicant: Chi-Wei Yang ,  Sheng-Yuan Tsai

Inventor： Chi-Wei Yang ,  Sheng-Yuan Tsai

IPC: H05K1/14

CPC classification number: G06F1/185 ,  G06F13/409 ,  H05K1/141 ,  H05K2201/10325 ,  H05K2201/10704

Abstract: Disclosed is a PCI mezzanine card (PMC) with pin-grid-array (PGA) which can be applied onto a two or more central processing unit (CPU) socket equipped mother board When one of the CPU sockets is not installed with a CPU, the PMC communicates with the mother board through the CPU socket with its PGA interface. An IC package mounted on the PMC can communicate with the mother board through the PMC.

Abstract translation: 公开了一种具有针阵列（PGA）的PCI夹层卡（PMC），可以应用于两个或更多个中央处理器（CPU）插座的母板上。当其中一个CPU插座没有安装CPU时， PMC通过带有PGA接口的CPU插座与主板通信。 安装在PMC上的IC封装可以通过PMC与母板通信。

公开(公告)号：US20060274513A1

公开(公告)日：2006-12-07

申请号：US11475405

申请日：2006-06-27

Applicant: Augusto Panella ,  John Lopata ,  James McGrath ,  Arindum Dutta

Inventor： Augusto Panella ,  John Lopata ,  James McGrath ,  Arindum Dutta

IPC: H05K7/06

CPC classification number: H05K1/0262 ,  H05K1/141 ,  H05K2201/10189 ,  H05K2201/10325 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: A processor mounted to a circuit board is provided with regulated voltage through lower-inductance circuit board traces by mounting a voltage regulator module for the processor, on the side of the circuit opposite to the processor. Current from the voltage regulator is provided to the processor by way of one or more conductors between the regulator and processor that extend through the circuit board from one side to the other. Inductance attributable to lead length is reduced by locating the voltage regulator close to its load. Circuit board space on the processor side of the circuit board is increased by moving the voltage regulator to the opposite side.

公开(公告)号：US07018219B2

公开(公告)日：2006-03-28

申请号：US10787647

申请日：2004-02-25

Applicant: Steven A. Rosenau

Inventor： Steven A. Rosenau

IPC: H01R12/00

CPC classification number: H05K1/112 ,  H05K1/0237 ,  H05K1/0298 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/049

Abstract: An electrical component, such as a trace, signal line, or contact pad connected to the trace or signal line, is covered by one or more layers. The electrical component is connected directly to an electrical device by forming an opening through the one or more layers. The opening exposes a portion of the electrical component. A connector, such as a solder ball, a pin contact, or a wire bond, is then attached to the exposed portion of the electrical component. The connector connects directly to another electrical device to create an electrical connection between the electrical component and the electrical device. The electrical device may be configured, for example, as a second signal line or contact pad in another stripline circuit, a microstrip circuit, an integrated circuit, or an electrical component.

Abstract translation: 连接到迹线或信号线的电气部件，例如迹线，信号线或接触焊盘，被一层或多层覆盖。 电气部件通过形成通过一个或多个层的开口直接连接到电气装置。 开口露出电气部件的一部分。 然后将诸如焊球，针接触或引线接合的连接器附接到电气部件的暴露部分。 连接器直接连接到另一个电气设备，以在电气部件和电气设备之间形成电连接。 电气设备可以被配置为例如另一个带状线电路中的第二信号线或接触焊盘，微带电路，集成电路或电气部件。

公开(公告)号：US07005736B2

公开(公告)日：2006-02-28

申请号：US10335368

申请日：2002-12-30

Applicant: Edward P. Osburn

Inventor： Edward P. Osburn

IPC: H01L23/48

CPC classification number: H05K1/0262 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

Abstract translation: 公开了一种用于改进对半导体器件的功率的传递和滤波的方法和装置，其通过组织用于以条形配置携带功率的互连（引脚，球，焊盘或其他互连），其缩短了功率之间所需的导电路径 源极和半导体器件，并且降低该导电路径的电阻。

公开(公告)号：US20060021795A1

公开(公告)日：2006-02-02

申请号：US10910506

申请日：2004-08-02

Applicant: Gregory Howard ,  Navin Kalidas ,  Paul Hundt ,  Gary Morrison

Inventor： Gregory Howard ,  Navin Kalidas ,  Paul Hundt ,  Gary Morrison

IPC: H01R12/04

CPC classification number: H05K3/3426 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K2201/10303 ,  H05K2201/10704 ,  H05K2201/10984 ,  Y02P70/613 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.

Abstract translation: 使用附着粘合剂（1103）将球栅阵列器件（1100）的半导体芯片（1101）安装到带基片（1102）上。 衬底（1102）的顶表面上的金属层使用其用于连接线（1104）的面积的约30％至90％，而仅用于构件/环（1105）和端子（1106）的剩余部分。 单层磁带封装上的差分对信号和大量信号的路由是可行的。 该实施例为芯片级设备创造了便宜的高性能带状球栅阵列封装。 端子（1106）将连接（通过接合电线或回流焊盘）连接到芯片接触焊盘。 插入在构件/环（1105）中的是用作焊料体/球（1108）的锚定件的导电销（1107）。 引脚（1107）对组装，测试和操作期间在装置（1100）中发生的热机械应力基本上不敏感。

公开(公告)号：US20060007638A1

公开(公告)日：2006-01-12

申请号：US11227087

申请日：2005-09-16

Applicant: Terumi Fujiyama ,  Kazuo Fukunaga ,  Morihiro Fukuda ,  Yoshiaki Kuwada ,  Hiromasa Mori ,  Yoshio Hashimoto

Inventor： Terumi Fujiyama ,  Kazuo Fukunaga ,  Morihiro Fukuda ,  Yoshiaki Kuwada ,  Hiromasa Mori ,  Yoshio Hashimoto

IPC: H01G9/00

CPC classification number: H01G4/40 ,  H01L23/66 ,  H01L24/81 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19103 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/162 ,  H05K2201/049 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/1059 ,  H05K2201/10689 ,  H05K2201/10704 ,  H01L2924/00

Abstract: A sheet capacitor of the invention has a contact portion formed in a through-hole requiring electrical connection with an IC connection pin among the through-holes in which the IC connection pins are inserted, and a capacitor element connected to the contact portion. Another sheet capacitor of the invention includes an insulating board and a capacitor element mounted on the insulating board. The insulating board has a connection land with an IC at the upper side, and a connection land with a printed wiring board at the lower side. The capacitor element and connection lands at the upper and lower side of the insulating board are connected with each other electrically. In any one of these configurations, a capacitor element of large capacity and low ESL is connected closely to the IC, and the mounting area of the peripheral circuits of the IC can be increased.

公开(公告)号：US06978539B2

公开(公告)日：2005-12-27

申请号：US10064462

申请日：2002-07-17

Applicant: Shao-Tsu Kung ,  Chen-Hua Liu

Inventor： Shao-Tsu Kung ,  Chen-Hua Liu

IPC: H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K3/303 ,  H05K1/0218 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/10598 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  Y10T29/49179

Abstract: A method for attaching an IC package to a circuit board, the IC package having a plurality of electrical contacts in an arrangement having a perimeter, first positions the IC package adjacent to the circuit board. Then, electrically connects the IC package to the circuit board through the plurality of electrical contacts. The method finally, disposes at least one anchor mechanically attaching the IC package to the circuit board, the anchor disposed at a location outside of the perimeter of the plurality of electrical contacts. The type, quantity, and exact geometry of the anchors depend on the specific design parameters of the IC package and circuit board.

Abstract translation: 一种用于将IC封装安装到电路板的方法，所述IC封装具有具有周边的布置的多个电触点，首先将IC封装定位成与电路板相邻。 然后，通过多个电触点将IC封装与电路板电连接。 该方法最终将至少一个锚定装置将IC封装机械地附接到电路板，该锚固件设置在多个电接触件的外围的位置。 锚的类型，数量和精确几何取决于IC封装和电路板的具体设计参数。

公开(公告)号：US06947293B2

公开(公告)日：2005-09-20

申请号：US10147138

申请日：2002-05-16

Applicant: Joseph Ted DiBene, II ,  David H. Hartke

Inventor： Joseph Ted DiBene, II ,  David H. Hartke

IPC: G06F1/18 ,  H01L23/427 ,  H01L23/433 ,  H01R4/64 ,  H01R12/16 ,  H05K1/02 ,  H05K1/14 ,  H05K3/30 ,  H05K3/36 ,  H05K7/10 ,  H05K7/20 ,  H05K1/11

CPC classification number: H05K7/1092 ,  G06F1/18 ,  G06F1/182 ,  G06F1/189 ,  H01L23/427 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01R4/64 ,  H01R12/52 ,  H01R12/7082 ,  H01R12/7088 ,  H01R12/721 ,  H05K1/0206 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/144 ,  H05K3/301 ,  H05K3/368 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/1053 ,  H05K2201/10598 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2201/2036 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A microprocessor packaging architecture using a modular circuit board assembly that provides power to a microprocessor while also providing for integrated thermal and electromagnetic interference (EMI) is disclosed. The modular circuit board assembly comprises a substrate, having a component mounted thereon, a circuit board, including a circuit for supplying power to the component, and at least one conductive interconnect device disposed between the substrate and the circuit board, the conductive interconnect device configured to electrically couple the circuit to the component.

Abstract translation: 公开了一种使用向微处理器供电并同时提供集成热和电磁干扰（EMI）的模块化电路板组件的微处理器封装结构。 所述模块化电路板组件包括具有安装在其上的部件的基板，包括用于向所述部件供电的电路的电路板以及设置在所述基板和所述电路板之间的至少一个导电互连装置，所述导电互连装置配置 以将电路电耦合到组件。