公开(公告)号：US10108366B2

公开(公告)日：2018-10-23

申请号：US15166268

申请日：2016-05-27

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Huei Huang ,  Yi-Lin Lai

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07 ,  G06F12/1009

Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.

公开(公告)号：US10095868B2

公开(公告)日：2018-10-09

申请号：US15380762

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57 ,  G06F9/4401 ,  H04L9/32 ,  G06F13/42 ,  G06F21/55

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an APIC access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

公开(公告)号：US20180267084A1

公开(公告)日：2018-09-20

申请号：US15984420

申请日：2018-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang ,  Wei-Cheng Chen

IPC: G01R1/073

CPC classification number: G01R1/07314 ,  G01R1/07378

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

公开(公告)号：US10079046B2

公开(公告)日：2018-09-18

申请号：US15389763

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F1/12 ,  G11C7/10 ,  G06F13/42 ,  G11C8/18 ,  G06F13/362 ,  G06F13/40

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a first mux, and where the plurality of successively delayed versions of the first signal comprises inputs to the first mux, and where the plurality of successively delayed versions comprises outputs of a first plurality of series-coupled matched inverter pairs. The gray encoder is configured to gray encode the propagation time to generate the value on the lag bus. The synchronous lag receiver is configured to receive one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. The synchronous lag receiver includes a second plurality of series-coupled matched inverter pairs, a second mux, and a bit receiver. The second plurality of series-coupled matched inverter pairs is configured to generate successively delayed versions of the data bit. The second mux is coupled to the second plurality of series-coupled matched inverter pairs, is configured to receive the value on the lag bus, and is configured to select one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver is configured to receive the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and is configured to register the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of radially distributed strobe signals.

公开(公告)号：US10074365B2

公开(公告)日：2018-09-11

申请号：US14226849

申请日：2014-03-27

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang

IPC: G10L15/22

CPC classification number: G10L15/22 ,  G10L2015/223

Abstract: A voice control method, a mobile terminal device, and a voice control system are provided. The voice control method includes the following steps. An application provides at least one operating parameter for a speech software development module. The speech software development module receives a voice signal and parses the voice signal, and thus a voice recognition result is obtained. The speech software development module determines whether the voice recognition result matches the operating parameters. When the voice recognition result matches the operating parameters, the speech software development module provides an operating signal for the application.

公开(公告)号：US20180254314A1

公开(公告)日：2018-09-06

申请号：US15971218

申请日：2018-05-04

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan LEE

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L28/10 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L29/0619

Abstract: A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.

公开(公告)号：US10049007B2

公开(公告)日：2018-08-14

申请号：US15243323

申请日：2016-08-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Jiangli Zhu ,  Ying Yu Tai

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The controller establishes a standard table and at least one priority table according to a read table stored in the non-volatile memory. The probability that the controller utilizes the read voltages corresponding to the indexes recorded in the priority table to read and successfully decode the codewords stored in non-volatile memory is high. When the controller utilizes the read voltages corresponding to the indexes recorded in the priority table to read and unsuccessfully decode the codewords, the controller utilizes the read voltages corresponding to the indexes recorded in the standard table to read and decode the codewords stored in non-volatile memory.

公开(公告)号：US09978384B2

公开(公告)日：2018-05-22

申请号：US14332670

申请日：2014-07-16

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yong Li ,  Zongpu Qi

IPC: G10L19/04 ,  G06F3/16 ,  G10L19/16 ,  H04M1/725

CPC classification number: G10L19/04 ,  G06F3/162 ,  G10L19/167 ,  H04M1/72558

Abstract: An electronic device is provided. The electronic device includes: a first processing unit; a storage unit, configured to store at least one audio file; a first memory unit; and a modulator-demodulator (modem), configured to perform audio processing of the electronic device during a phone call, wherein when the electronic device is used to play the audio file, the first processing unit reads the audio file from the storage unit, retrieves header information of the audio file, and writes the audio file into the first memory unit, wherein the modem accesses the audio file stored in the first memory unit based on the header information, and performs audio decoding on the audio file.

公开(公告)号：US09971605B2

公开(公告)日：2018-05-15

申请号：US14281709

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/44 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

公开(公告)号：US20180101314A1

公开(公告)日：2018-04-12

申请号：US15287743

申请日：2016-10-07

Applicant: VIA Technologies, Inc.

Inventor： Ying-Yu Tai ,  Jiangli Zhu ,  Jiin Lai

IPC: G06F3/06 ,  G06F12/1009

Abstract: A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.