公开(公告)号：US20190393192A1

公开(公告)日：2019-12-26

申请号：US16014313

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/427 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

公开(公告)号：US20190385933A1

公开(公告)日：2019-12-19

申请号：US16007269

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/473 ,  H01L25/065 ,  H01L23/467 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

公开(公告)号：US20190385931A1

公开(公告)日：2019-12-19

申请号：US16007255

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/473 ,  H01L25/065 ,  H01L23/467 ,  H01L23/367 ,  H01L23/498

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

公开(公告)号：US20190343017A1

公开(公告)日：2019-11-07

申请号：US15970420

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H05K7/20 ,  H01L23/427 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.

公开(公告)号：US20190326192A1

公开(公告)日：2019-10-24

申请号：US15957437

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: A heat dissipation device may be formed as a thermally conductive structure having at least one thermal isolation structure extending at least partially through the thermally conductive structure. The heat dissipation device may be thermally connected to a plurality of integrated circuit devices, such that the at least one thermal isolation structure is positioned between at least two integrated circuit devices. The heat dissipation device allows for heat transfer away from each of the plurality of integrated circuit devices, such as in a z-direction within the thermally conductive structure, while substantially preventing heat transfer in either the x-direction and/or the y-direction within the thermally isolation structure, such that thermal cross-talk between integrated circuit devices is reduced.

公开(公告)号：US10186465B2

公开(公告)日：2019-01-22

申请号：US15748138

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel A. Elsherbini ,  Henning Braunisch ,  Yidnekachew S. Mekonnen ,  Krishna Bharath ,  Mathew J. Manusharow ,  Aleksandar Aleksov ,  Nathan Fritz

IPC: H01L23/14 ,  H01L23/12 ,  H01L23/473 ,  H01L21/48 ,  H01L23/538 ,  H01L23/492

Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.

公开(公告)号：US20180287115A1

公开(公告)日：2018-10-04

申请号：US15475751

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Veronica A. Strong ,  Sasha N. Oster ,  Feras Eid ,  Aranzazu Maestre Caro

IPC: H01M2/10 ,  H01M4/70 ,  H01M4/66 ,  H01M4/04 ,  C23C18/38 ,  C23C18/18 ,  C23C18/16 ,  A41D1/00 ,  A61B5/00

CPC classification number: H01M2/1066 ,  A41D1/002 ,  A61B5/01 ,  A61B5/024 ,  A61B5/14532 ,  A61B5/4266 ,  A61B5/6804 ,  B32B5/24 ,  C23C18/1641 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/38 ,  G06F1/163 ,  H01L23/5387 ,  H01M4/0402 ,  H01M4/661 ,  H01M10/0422 ,  H01M10/0436 ,  H01M2220/30 ,  H05K1/038 ,  H05K2201/10037

Abstract: An apparatus system is provided which comprises: a fabric; a self-assembled monolayer (SAM) material formed on the fabric; and a battery cell formed on the fabric, wherein a current collector of the battery cell is at least in part formed on the SAM material.

公开(公告)号：US10083923B2

公开(公告)日：2018-09-25

申请号：US14860614

申请日：2015-09-21

Applicant: INTEL CORPORATION

Inventor： Georgios C. Dogiamis ,  Sasha N. Oster ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Brandon M. Rawlings ,  Feras Eid

IPC: H01L23/58 ,  H01L23/66 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/014 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/00014

Abstract: Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

公开(公告)号：US09902152B2

公开(公告)日：2018-02-27

申请号：US15199899

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff ,  Sasha N. Oster ,  Thomas L. Sounart ,  Georgios C. Dogiamis ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: B41J2/14

CPC classification number: B41J2/14298 ,  B41J2/14201 ,  B41J2/14233 ,  B41J2002/14266 ,  B41J2202/13

Abstract: Embodiments of the invention include a piezoelectric package integrated jet device. In one example, the jet device includes a vibrating membrane positioned between first and second cavities of an organic substrate, a piezoelectric material coupled to the vibrating membrane which acts as a first electrode, and a second electrode in contact with the piezoelectric material. The vibrating membrane generates fluid flow through an orifice in response to application of an electrical signal between the first and second electrodes.

公开(公告)号：US20180026730A1

公开(公告)日：2018-01-25

申请号：US15676611

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sasha N. Oster ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Kumar Ranganathan ,  Wen-Ling M. Huang

IPC: H04B13/00 ,  A61M5/142 ,  A61B5/00 ,  A61B5/145 ,  A61N1/04 ,  A61B5/11 ,  A61B5/0402 ,  A61B5/01 ,  H04B5/00 ,  A61N7/00 ,  A61B5/021

CPC classification number: H04B13/005 ,  A61B5/0024 ,  A61B5/01 ,  A61B5/0205 ,  A61B5/021 ,  A61B5/0402 ,  A61B5/0432 ,  A61B5/1102 ,  A61B5/1107 ,  A61B5/1121 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/4839 ,  A61B5/4869 ,  A61B5/6833 ,  A61F7/007 ,  A61M5/14248 ,  A61N1/0484 ,  A61N1/0492 ,  A61N1/3603 ,  A61N7/00 ,  H04B5/0012

Abstract: Discussed generally herein are methods and devices including or providing a patch system that can help in diagnosing a medical condition and/or provide therapy to a user. A body-area network can include a plurality of communicatively coupled patches that communicate with an intermediate device. The intermediate device can provide data representative of a biological parameter monitored by the patches to proper personnel, such as for diagnosis and/or response.