Assembly of Electronic and Optical Devices
    11.
    发明申请
    Assembly of Electronic and Optical Devices 有权
    电子和光学设备的组装

    公开(公告)号:US20130283591A1

    公开(公告)日:2013-10-31

    申请号:US13486573

    申请日:2012-06-01

    Abstract: A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component.

    Abstract translation: 一种用于操作组装工具的方法包括:在装配表面上拆卸第一部件,其中操纵器的第一工具尖端具有由平面和基本垂直于该平面的轴限定的运动范围, 组装表面,使组装表面相对于轴线从第一方向改变到第二方向,使第一部件从组装表面用操纵器的第二工具尖端提升,并将第一部件放置在第二部件上。

    Assembly of Electronic and Optical Devices
    12.
    发明申请
    Assembly of Electronic and Optical Devices 有权
    电子和光学设备的组装

    公开(公告)号:US20130283584A1

    公开(公告)日:2013-10-31

    申请号:US13459460

    申请日:2012-04-30

    Abstract: An assembly tool apparatus includes a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, a jig having an assembly surface operative to move from a first orientation relative to the axis to a second orientation relative to the axis, a first tool tip operative to engage with and be positioned by the manipulator, and a second tool tip operative to engage with and be positioned by the manipulator.

    Abstract translation: 装配工具装置包括具有由平面限定的运动范围和基本上垂直于该平面的轴线的运动范围的操纵器,具有可相对于轴线从第一方向相对于轴线移动到第二取向的组装表面的夹具 所述轴线,操作成与所述操纵器接合并由所述操纵器定位的第一工具尖端以及与所述操纵器接合并由所述操纵器定位的第二工具尖端。

    Integrated circuit (IC) test probe
    13.
    发明授权
    Integrated circuit (IC) test probe 有权
    集成电路(IC)测试探头

    公开(公告)号:US08525168B2

    公开(公告)日:2013-09-03

    申请号:US13179868

    申请日:2011-07-11

    Abstract: A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 μm). The probe tips may be stiffened with SiO2 (and optionally silicon) extending along the sidewalls. A redistribution layer connects individual test probe tips externally. The probe tips may be capped with a hardening cap that also caps stiffening SiO2 and silicon along the tip sidewall.

    Abstract translation: 用于探测集成电路(IC)芯片的测试头和制造测试头的方法。 测试头包括穿过半导体层(例如硅层)并离开半导体层(例如硅层)的一个表面的通孔阵列(例如,环形通孔或分组的矩形通孔)。 通孔,单独的测试探针尖端可以在等于或小于50微米(50um)的间距上。 探针尖端可以用沿着侧壁延伸的SiO 2(和任选的硅)加强。 再分配层外部连接各个测试探针。 探针尖端可以用硬化帽盖住,硬化帽也可以沿着尖端侧壁封闭加强SiO 2和硅。

    PROCESS FOR MAPPING FORMIC ACID DISTRIBUTION
    14.
    发明申请
    PROCESS FOR MAPPING FORMIC ACID DISTRIBUTION 失效
    映射酸性分布的方法

    公开(公告)号:US20120261458A1

    公开(公告)日:2012-10-18

    申请号:US13089074

    申请日:2011-04-18

    Abstract: A transfer process for bonding a solderable device to a solderable first substrate having a first oxidized surface comprises placing the solderable device proximate to the first substrate in a reducing chamber, where the first surface cannot be visually observed. We place a second substrate having a second oxidized surface in the chamber in a way to visually observe the second surface. Selecting the first substrate and the second substrate so that the reduction of the second surface correlates with the reduction of the first surface provides an indication of the degree of reduction of the first surface. Introducing a reducing agent into the chamber under reducing conditions reduces the surfaces which we track by irradiating and observing the second surface; evaluate any change in the second surface during irradiation and correlate the change with first surface reduction. When sufficiently reduced, we solder the first substrate to the device.

    Abstract translation: 用于将可焊接装置接合到具有第一氧化表面的可焊接的第一基板的转移过程包括将可焊接装置靠近第一基板放置在还原室中,其中第一表面不能被目视观察。 我们以在目视上观察第二表面的方式放置在腔室中具有第二氧化表面的第二衬底。 选择第一基板和第二基板,使得第二表面的减小与第一表面的减小相关,提供第一表面的减小程度的指示。 在还原条件下将还原剂引入到室中通过照射和观察第二表面来减少我们跟踪的表面; 评估照射期间第二表面的任何变化,并将变化与第一表面还原相关联。 当充分减少时,我们将第一个衬底焊接到器件。

    Laser Ablation for Integrated Circuit Fabrication
    16.
    发明申请
    Laser Ablation for Integrated Circuit Fabrication 有权
    激光消融用于集成电路制造

    公开(公告)号:US20110290406A1

    公开(公告)日:2011-12-01

    申请号:US12788843

    申请日:2010-05-27

    Abstract: A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

    Abstract translation: 一种用于从晶片释放处理器的方法,包括集成电路(IC)的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂,其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。 一种用于从晶片释放处理器的系统,包括IC的晶片包括使用包含聚合物的粘合剂连接到晶片的处理器; 边缘处理模块,所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器,激光器被配置为通过处理器消融粘合剂。

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