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53 条记录 (耗时 0.024 秒)

    Structure and method for a fishbone differential capacitor
    12.
    发明授权
    Structure and method for a fishbone differential capacitor 有权
    鱼骨差分电容器的结构和方法

    公开(公告)号：US08860114B2

    公开(公告)日：2014-10-14

    申请号：US13411052

    申请日：2012-03-02

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    IPC分类号： H01L29/92

    CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L28/88 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.

    摘要翻译： 本发明提供集成电路。 集成电路包括具有由第一轴线和垂直于第一轴线的第二轴线限定的表面的基板; 以及设置在基板上的电容器结构。 电容器结构包括第一导电元件; 对称地配置在第一导电部件的相对侧上的第二导电部件和第三导电部件。 第一，第二和第三导电部件通过相应的介电材料彼此分离。

    Apparatus and methods for de-embedding through substrate vias
    13.
    发明授权
    Apparatus and methods for de-embedding through substrate vias 有权
    用于通过衬底通孔去嵌入的装置和方法

    公开(公告)号：US08809073B2

    公开(公告)日：2014-08-19

    申请号：US13197602

    申请日：2011-08-03

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Victor Chih Yuan Chang ,  Min-Chie Jeng

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Victor Chih Yuan Chang ,  Min-Chie Jeng

    IPC分类号： H01L21/66 ,  G01R31/26

    CPC分类号： G01R31/2644 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

    摘要翻译： 一种方法包括在具有至少两个通过衬底通孔（“TSV”）的衬底上提供多个测试结构，用于对包括至少两个TSV的待测器件（DUT）的固有特性的测量进行解嵌入; 测量包括与长度为L的传输线耦合的两个焊盘的衬底上的第一和第二测试结构的固有特性[L] 使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解焊盘和传输线的固有特性; 使用焊盘和传输线的固有特性来解嵌第三和第四测试结构的测量; 并且对于BM_L和BM_LX使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解TSV的固有特性。

    Integrated antenna structure on separate semiconductor die
    14.
    发明授权
    Integrated antenna structure on separate semiconductor die 有权
    集成天线结构在单独的半导体芯片上

    公开(公告)号：US08754818B2

    公开(公告)日：2014-06-17

    申请号：US13541937

    申请日：2012-07-05

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

    IPC分类号： H01Q1/12 ,  H01Q1/38 ,  H01Q1/40

    CPC分类号： H01Q1/38 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01Q1/2283 ,  H01Q1/40 ,  H01Q7/00 ,  H01L2924/00

    摘要： Some embodiments relate to a semiconductor module comprising an integrated antenna structure configured to wirelessly transmit signals. The integrated antenna structure has a lower metal layer and an upper metal layer. The lower metal layer is disposed on a lower die and is connected to a ground terminal. The upper metal layer is disposed on an upper die and is connected to a signal generator configured to generate a signal to be wirelessly transmitted. The upper die is stacked on the lower die and is connected to the lower die by way of an adhesion layer having one or more micro-bumps. By connecting the lower and upper die together by way of the adhesion layer, the lower and upper metal layers are separated from each other by a large spacing that provides for a good performance of the integrated antenna structure.

    摘要翻译： 一些实施例涉及包括被配置为无线传输信号的集成天线结构的半导体模块。 集成天线结构具有下金属层和上金属层。 下金属层设置在下模上并连接到接地端子。 上金属层设置在上模上并连接到被配置为产生要无线传输的信号的信号发生器。 上模具堆叠在下模上，并通过具有一个或多个微凸块的粘合层连接到下模。 通过将粘合层连接在一起，下部和上部金属层彼此间隔开大间隔，从而提供了集成天线结构的良好性能。

    Voltage-controlled oscillator
    15.
    发明授权
    Voltage-controlled oscillator 有权
    压控振荡器

    公开(公告)号：US08665030B2

    公开(公告)日：2014-03-04

    申请号：US13325442

    申请日：2011-12-14

    申请人： Ying-Ta Lu ,  Hsien-Yuan Liao ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Ying-Ta Lu ,  Hsien-Yuan Liao ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1852

    摘要： A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit.

    摘要翻译： 压控振荡器电路包括第一晶体管，第二晶体管，第一谐振器电路，第二谐振器电路，第一电流路径和第二电流路径。 第一晶体管的漏极耦合到第二晶体管的栅极和第一谐振器电路的第一端。 第一晶体管的源极耦合到第一电流路径和第二谐振器电路的第一端。 第二晶体管的漏极耦合到第一晶体管的栅极和第一谐振器电路的第二端。 第二晶体管的源极耦合到第二电流路径和第二谐振器电路的第二端。

    Adjustable Meander Line Resistor
    16.
    发明申请
    Adjustable Meander Line Resistor 有权
    可调式曲折线电阻

    公开(公告)号：US20130200447A1

    公开(公告)日：2013-08-08

    申请号：US13365021

    申请日：2012-02-02

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L27/088

    CPC分类号： H01L23/5228 ,  H01L23/647 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/10897 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor formed on a second doped region of the transistor and a connector coupled between the first resistor and the second resistor. A control circuit is employed to control the on and off of the transistor so as to achieve the adjustable meander line resistor.

    摘要翻译： 可调式曲折线电阻器包括多个串联电路。 每个串联电路包括形成在晶体管的第一掺杂区域上的第一电阻器，形成在晶体管的第二掺杂区域上的第二电阻器和耦合在第一电阻器和第二电阻器之间的连接器。 采用控制电路来控制晶体管的导通和截止，从而实现可调谐的曲折线电阻。

    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE
    17.
    发明申请
    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE 有权
    集成电路接地屏蔽结构

    公开(公告)号：US20130147023A1

    公开(公告)日：2013-06-13

    申请号：US13313240

    申请日：2011-12-07

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H01L23/552

    CPC分类号： H01L23/5227 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译： 本公开提供了一种集成电路（IC）装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽（PGS）结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。

    DE-EMBEDDING ON-WAFER DEVICES
    20.
    发明申请
    DE-EMBEDDING ON-WAFER DEVICES 有权
    嵌入式嵌入式设备

    公开(公告)号：US20120146680A1

    公开(公告)日：2012-06-14

    申请号：US12963511

    申请日：2010-12-08

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Sa-Lly Liu

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Sa-Lly Liu

    IPC分类号： G01R31/00

    CPC分类号： G01R31/2601 ,  G01R1/0491 ,  G01R31/2644 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/5602 ,  H01L22/34

    摘要： A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.

    摘要翻译： 提供传输线。 在一个实施例中，传输线包括衬底，衬底内的阱，阱上的屏蔽层以及屏蔽层上的多个中间金属层，多个中间金属层通过多个通孔耦合。 传输线还包括多个中间金属层上的顶部金属层。 还公开了用于去嵌入晶片装置和晶片的测试结构。