公开(公告)号：US20140171751A1

公开(公告)日：2014-06-19

申请号：US13719360

申请日：2012-12-19

Applicant: Robert L. Sankman ,  Ian A. Young ,  Johanna M. Swan ,  Marko Radosavljevic

Inventor： Robert L. Sankman ,  Ian A. Young ,  Johanna M. Swan ,  Marko Radosavljevic

IPC: A61B5/0205 ,  A61B5/024 ,  A61B5/145 ,  A61B5/021 ,  A61B5/0488 ,  A61N5/00 ,  A61B5/01 ,  A61B5/0245 ,  A61N1/36 ,  A61N5/06 ,  A61H99/00 ,  A61B5/00 ,  A61B5/0476

CPC classification number: A61B5/02055 ,  A61B5/0002 ,  A61B5/0004 ,  A61B5/0006 ,  A61B5/0008 ,  A61B5/0205 ,  A61B5/021 ,  A61B5/02438 ,  A61B5/0245 ,  A61B5/0476 ,  A61B5/0488 ,  A61B5/14532 ,  A61B5/14542 ,  A61B5/4839 ,  A61B5/681 ,  A61H23/02 ,  A61H2201/501 ,  A61H2201/5097 ,  A61H2230/06 ,  A61H2230/10 ,  A61H2230/202 ,  A61H2230/30 ,  A61H2230/50 ,  A61H2230/60 ,  A61N1/36003 ,  A61N1/37229 ,  A61N1/37282

Abstract: Described herein are technologies related to a wireless electronic vital sign monitoring of a person. More particularly, detecting vital signs and processing of the detected vital signs using a bio monitoring patch.

Abstract translation: 这里描述了与人的无线电子生命体征监测有关的技术。 更具体地，使用生物监测补片检测生命体征并检测检测到的生命体征。

公开(公告)号：US20140103397A1

公开(公告)日：2014-04-17

申请号：US14141648

申请日：2013-12-27

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract translation: 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20140091308A1

公开(公告)日：2014-04-03

申请号：US13631534

申请日：2012-09-28

Applicant: Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz KABEHIE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz KABEHIE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US20140084387A1

公开(公告)日：2014-03-27

申请号：US13627971

申请日：2012-09-26

Applicant: Gilbert DEWEY ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Scott B. CLENDENNING ,  Ravi PILLARISETTY

Inventor： Gilbert DEWEY ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Scott B. CLENDENNING ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66803 ,  B82Y10/00 ,  H01L21/2233 ,  H01L21/228 ,  H01L21/28264 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract translation: 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。

公开(公告)号：US20140084246A1

公开(公告)日：2014-03-27

申请号：US13629178

申请日：2012-09-27

Applicant: Ravi Pillarisetty ,  Niti Goel ,  Han Wui Then ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

Inventor： Ravi Pillarisetty ,  Niti Goel ,  Han Wui Then ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC: H01L29/78 ,  H01L29/775

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/785 ,  H01L29/78696

Abstract: Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

Abstract translation: 描述具有底层寄生泄漏阻挡层的具有锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的第一缓冲层。 寄生泄漏屏障设置在第一缓冲层之上。 第二缓冲层设置在寄生泄漏屏障的上方。 锗活性层设置在第二缓冲层上方。 栅电极堆叠设置在锗活性层上方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的寄生泄漏屏障之上。

公开(公告)号：US20140084239A1

公开(公告)日：2014-03-27

申请号：US13629148

申请日：2012-09-27

Applicant: Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Dipanjan Basu ,  Sanaz K. Gardner ,  Satyarth Suri ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Han Wui Then ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Dipanjan Basu ,  Sanaz K. Gardner ,  Satyarth Suri ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Han Wui Then ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/201 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.

Abstract translation: 描述具有低带隙包层的沟道区的非平面半导体器件。 例如，半导体器件包括布置在衬底上方的多个纳米线的垂直布置。 每个纳米线包括具有第一带隙的内部区域和围绕内部区域的外部包层。 包层具有第二较低带隙。 栅堆叠设置在每个纳米线的沟道区上并完全包围。 栅极堆叠包括设置在包层上并围绕着包层的栅极电介质层和设置在栅极介电层上的栅电极。 源区和漏区设置在纳米线的沟道区的两侧。

公开(公告)号：US20140054548A1

公开(公告)日：2014-02-27

申请号：US14069880

申请日：2013-11-01

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

IPC: H01L29/775 ,  H01L21/76 ,  H01L29/66

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20140035041A1

公开(公告)日：2014-02-06

申请号：US13997972

申请日：2011-12-28

Applicant: Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

Inventor： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC: H01L29/78 ,  H01L29/66 ,  G11C11/412

CPC classification number: H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130277683A1

公开(公告)日：2013-10-24

申请号：US13976837

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 10) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性结晶半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（10 10）面在硅的（110）平面上。

公开(公告)号：US20130270512A1

公开(公告)日：2013-10-17

申请号：US13976411

申请日：2011-12-19

Applicant: Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.