公开(公告)号：US20140091308A1

公开(公告)日：2014-04-03

申请号：US13631534

申请日：2012-09-28

申请人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz KABEHIE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

发明人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz KABEHIE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

摘要翻译： 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US20140091360A1

公开(公告)日：2014-04-03

申请号：US13630527

申请日：2012-09-28

申请人： Ravi PILLARISETTY ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. CHAU

发明人： Ravi PILLARISETTY ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. CHAU

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/336

CPC分类号： H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

摘要翻译： 沟槽限制的选择性外延生长工艺，其中半导体器件层的外延生长在沟槽的范围内进行。 在实施例中，制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。 接种表面周围的半导体区域可以相对于接种表面凹陷，其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。 在形成沟槽的实施例中，牺牲性硬掩模翅片可以被覆盖在电介质中，然后将其平坦化以暴露硬掩模翅片，然后将其去除以暴露接种表面。 通过选择性异质外延从种子表面形成半导体器件层。 在实施例中，通过使隔离电介质的顶表面凹陷，从半导体器件层形成非平面器件。 在实施例中，可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。

公开(公告)号：US20140291726A1

公开(公告)日：2014-10-02

申请号：US14302350

申请日：2014-06-11

申请人： Ravi Pillarisetty ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. Chau

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

公开(公告)号：US20170069596A1

公开(公告)日：2017-03-09

申请号：US15121759

申请日：2014-03-27

申请人： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

发明人： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC分类号： H01L25/065 ,  H01L29/24 ,  H01L29/20 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L25/0652 ,  G06F1/1652 ,  G09F9/301 ,  G09G3/3648 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/4985 ,  H01L25/00 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/24 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002

摘要： Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了芯片上的多设备灵活系统（SOC）以及用于制造这种SOC的方法。 可以依次处理多材料堆叠，以在单个柔性SOC中形成多个集成电路（IC）装置。 通过从单个堆叠形成IC器件，可以通过单个金属化工艺为多个器件形成触点，并且可以将这些触点位于SOC的公共背面中。 堆叠层可以根据处理温度进行排序和处理，使得较早进行较高温度处理。 以这种方式，堆叠的中间层可以屏蔽一些堆叠层与处理堆叠的上层相关联的升高的处理温度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140094223A1

公开(公告)日：2014-04-03

申请号：US13631514

申请日：2012-09-28

申请人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU

发明人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L23/535 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66545

摘要： Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.

摘要翻译： 实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。 在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。 这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。 使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

公开(公告)号：US20140170998A1

公开(公告)日：2014-06-19

申请号：US13720852

申请日：2012-12-19

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC分类号： H01L29/80 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

摘要： A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20140175515A1

公开(公告)日：2014-06-26

申请号：US13725546

申请日：2012-12-21

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Robert S. CHAU

IPC分类号： H01L29/772 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

摘要翻译： III-N半导体通道在过渡层和III-N偏振层之间组成分级。 在实施例中，栅堆叠沉积在包括渐变III-N半导体沟道的鳍的侧壁上，允许在响应于栅极偏置电压的至少两个侧壁表面相邻的III-N半导体沟道中形成传输沟道。 在实施例中，栅极叠层完全沉积在包括III-N半导体沟道的纳米线周围，该纳米线被组成分级，以使得能够响应于栅极形成与偏振层和过渡层两者相邻的III-N半导体沟道中的传输沟道 偏压。

公开(公告)号：US20160204276A1

公开(公告)日：2016-07-14

申请号：US14912403

申请日：2013-09-25

申请人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert CHAU

发明人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert CHAU

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L29/06

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78681

摘要： Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

摘要翻译： 描述了形成高电压（111）硅纳米结构的方法。 这些方法和结构可以包括在硅鳍结构的（111）表面上形成III-V器件层，在III-V器件层上形成2DEG诱导极化层，在III部分上形成源极/漏极材料 -V在硅片末端的器件层。 源极和漏极区域之间的硅鳍结构的中间部分可以被去除，并且用电介质材料回填，然后可以在III-V器件层上形成栅极电介质和栅极材料。

公开(公告)号：US20140084387A1

公开(公告)日：2014-03-27

申请号：US13627971

申请日：2012-09-26

申请人： Gilbert DEWEY ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Scott B. CLENDENNING ,  Ravi PILLARISETTY

发明人： Gilbert DEWEY ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Scott B. CLENDENNING ,  Ravi PILLARISETTY

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66803 ,  B82Y10/00 ,  H01L21/2233 ,  H01L21/228 ,  H01L21/28264 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

摘要： A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

摘要翻译： 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。

公开(公告)号：US20200211842A1

公开(公告)日：2020-07-02

申请号：US16232535

申请日：2018-12-26

申请人： Glenn GLASS ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Anand MURTHY ,  Walid HAFEZ

发明人： Glenn GLASS ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Anand MURTHY ,  Walid HAFEZ

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L27/092 ,  H01L23/00 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8252

摘要： An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.