公开(公告)号：US20150137259A1

公开(公告)日：2015-05-21

申请号：US14453705

申请日：2014-08-07

Applicant: Hauk HAN ,  Yu Min KIM ,  Ki Hyun YOON ,  Myoung Bum LEE ,  Chang Won LEE ,  Joo Yeon HA

Inventor： Hauk HAN ,  Yu Min KIM ,  Ki Hyun YOON ,  Myoung Bum LEE ,  Chang Won LEE ,  Joo Yeon HA

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/45

CPC classification number: H01L29/4175 ,  H01L21/76856 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a conductive region, an insulating layer disposed on the substrate and including an opening exposing the conductive region, and a conductive layer buried within the opening and including a first region disposed on inner side walls of the opening and a second region disposed within the first region. The first region includes a plurality of first crystal grains and the second region includes a plurality of second crystal grains. The pluralities of first and second crystal grains are separated from each other at a boundary formed between the first and second regions.

Abstract translation: 一种半导体器件包括：衬底，其包括导电区域，绝缘层设置在衬底上并且包括暴露导电区域的开口;以及导电层，其被埋在开口内，并且包括设置在开口的内侧壁上的第一区域和 第二区域设置在第一区域内。 第一区域包括多个第一晶粒，第二区域包括多个第二晶粒。 多个第一和第二晶粒在第一和第二区域之间形成的边界处彼此分离。

公开(公告)号：US20150064885A1

公开(公告)日：2015-03-05

申请号：US14309018

申请日：2014-06-19

Applicant: Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

Inventor： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

Abstract translation: 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

公开(公告)号：US08923057B2

公开(公告)日：2014-12-30

申请号：US12981625

申请日：2010-12-30

Applicant: Yong-Hoon Son ,  Myoung Bum Lee ,  Ki Hyun Hwang ,  Seung Jae Baik

Inventor： Yong-Hoon Son ,  Myoung Bum Lee ,  Ki Hyun Hwang ,  Seung Jae Baik

IPC: G11C16/04 ,  H01L29/66 ,  H01L27/115 ,  G11C5/04 ,  G11C5/06

CPC classification number: H01L27/11551 ,  G11C5/04 ,  G11C5/063 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Abstract translation: 三维半导体器件包括在基板上二维布置的有源图案，三维地布置在有源图案之间的电极以及三维地布置在由有源图案和电极限定的交叉点处的存储区域。 每个有源图案用作用于与形成在与基板相同的高度处的两个不同存储区域的电连接的公共电流路径。

公开(公告)号：US07790591B2

公开(公告)日：2010-09-07

申请号：US12270014

申请日：2008-11-13

Applicant: Dong-chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

Inventor： Dong-chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/31616 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3145 ,  H01L21/31604

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Abstract translation: 提供了制造半导体器件的方法，包括在半导体衬底上的栅极绝缘层上形成电荷存储层。 在电荷存储层上形成阻挡绝缘层，在隔离绝缘层上形成电极层。 阻挡绝缘层可以通过在第一温度下形成下部金属氧化物层并在低于第一温度的第二温度下在下部金属氧化物层上形成上部金属氧化物层而形成。

公开(公告)号：US07585756B2

公开(公告)日：2009-09-08

申请号：US11839387

申请日：2007-08-15

Applicant: Gab-Jin Nam ,  Myoung-Bum Lee

Inventor： Gab-Jin Nam ,  Myoung-Bum Lee

IPC: H01L21/3205

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78

Abstract: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Abstract translation: MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。 栅电极包括第一栅极导电层图案和第二栅极导电层图案。 第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。 第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

公开(公告)号：US20080067581A1

公开(公告)日：2008-03-20

申请号：US11896834

申请日：2007-09-06

Applicant: Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

Inventor： Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal

Abstract translation: 非易失性存储器件包括在衬底的通道区域上的隧道绝缘层图案，隧道绝缘层图案上的电荷俘获层图案，电荷俘获层图案上的阻挡层图案，以及包括导电 阻挡层图案上的层图案和导电层图案上的阻挡层图案。 导电层图案包括金属

公开(公告)号：US20080042173A1

公开(公告)日：2008-02-21

申请号：US11839387

申请日：2007-08-15

Applicant: Gab-Jin NAM ,  Myoung-Bum LEE

Inventor： Gab-Jin NAM ,  Myoung-Bum LEE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78

Abstract: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Abstract translation: MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。 栅电极包括第一栅极导电层图案和第二栅极导电层图案。 第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。 第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

公开(公告)号：US07176533B2

公开(公告)日：2007-02-13

申请号：US10982113

申请日：2004-11-04

Applicant: Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

Inventor： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

IPC: H01L29/76

CPC classification number: H01L21/76877 ,  H01L21/2257 ,  H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract translation: 形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。 可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。 还讨论了相关结构。

公开(公告)号：US06953741B2

公开(公告)日：2005-10-11

申请号：US10634168

申请日：2003-08-05

Applicant: Eun-ae Chung ,  Myoung-bum Lee ,  Beom-jun Jim

Inventor： Eun-ae Chung ,  Myoung-bum Lee ,  Beom-jun Jim

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/04

CPC classification number: H01L21/28525 ,  H01L21/28512 ,  H01L21/76877 ,  H01L21/76886

Abstract: Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped with a gas containing an element of the first impurity type and a contact plug is formed in the contact hole. Contact structure for a semiconductor device are also provided that include an interlayer dielectric of the semiconductor device having a contact hole formed therein that exposes a silicon-based region of a first impurity type. A delta-doped region of the first impurity type is provided in the exposed silicon-based region. A contact plug is provided in the contact hole and on the delta-doped region.

Abstract translation: 通过对半导体器件的层间电介质进行构图以形成露出第一杂质型硅基区域的接触孔来提供制造半导体器件的接触的方法。 暴露的硅基区域掺杂含有第一杂质类型的元素的气体，并且接触孔形成在接触孔中。 还提供了一种半导体器件的接触结构，其包括半导体器件的层间电介质，其具有在其中形成的接触孔，其暴露第一杂质类型的硅基区域。 在暴露的硅基区域中提供第一杂质类型的δ掺杂区域。 在接触孔和δ掺杂区域上提供接触塞。

公开(公告)号：US06787468B2

公开(公告)日：2004-09-07

申请号：US10035257

申请日：2002-01-04

Applicant: Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

Inventor： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC: H01L2144

CPC classification number: H01L21/76844 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76882 ,  H01L2221/1089

Abstract: A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

Abstract translation: 一种制造在硅衬底上的绝缘层中具有凹陷区域的半导体器件的方法，包括以下步骤：在包括凹陷区域中的衬底表面的绝缘层的整个表面上沉积阻挡金属， 在凹陷区域之外的阻挡金属上的成核层，在凹陷区域中的阻挡金属上沉积CVD-Al层，在抗成核层和除了在...中形成的阻挡金属之外沉积抑制铝迁移的金属或金属合金 并且沉积PVD-Al层并再次流动PVD-Al层，以改善铝槽的质量。 本方法抑制PVD-Al迁移和晶粒生长，这导致防止半导体器件中的异常图案化。