公开(公告)号：US09766936B2

公开(公告)日：2017-09-19

申请号：US14935056

申请日：2015-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

公开(公告)号：US09507410B2

公开(公告)日：2016-11-29

申请号：US14310908

申请日：2014-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

公开(公告)号：US09372803B2

公开(公告)日：2016-06-21

申请号：US13722808

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Srilatha Manne ,  Michael Schulte ,  Lloyd Bircher ,  Madhu Saravana Sibi Govindan ,  Yasuko Eckert

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0806 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract translation: 提出了一种系统和方法。 一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为 处于修改状态。 通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度， 与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

公开(公告)号：US09367455B2

公开(公告)日：2016-06-14

申请号：US14018562

申请日：2013-09-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Lena E. Olson ,  Srilatha Manne ,  James M. O'Connor

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0802 ,  G06F9/3834 ,  G06F9/3838 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/6022 ,  G06F2212/6032 ,  Y02D10/13

Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.

Abstract translation: 所描述的实施例包括使用对存储到负载转发的预测的核心。 在所描述的实施例中，核心包括加载存储单元，存储缓冲器和预测机制。 在运行期间，预测机制产生一个预测，即使用从存储缓冲器转发的数据来满足负载，因为负载从栈中的存储器位置加载数据。 基于该预测，加载存储单元首先向存储缓冲器发送对数据的请求，以尝试使用从存储缓冲器转发的数据来满足负载。 如果从存储缓冲区返回数据，则使用该数据来满足负载。 然而，如果使用从存储缓冲器转发的数据来满足负载的尝试不成功，则加载存储单元然后分别向缓存发送用于满足负载的数据请求。

公开(公告)号：US20160086654A1

公开(公告)日：2016-03-24

申请号：US14492045

申请日：2014-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan Jayasena ,  Dong Ping Zhang

IPC: G11C11/4096 ,  G11C5/02 ,  G11C11/4078

CPC classification number: G11C11/4096 ,  G11C5/025 ,  G11C7/04 ,  G11C8/12

Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Abstract translation: 管理存储器系统中的热水平的方法可以包括确定与存储器结构中的多个位置中的每一个相关联的预期热水平，以及针对存储器结构的多个操作的每个操作，将操作分配给 基于与操作相关联的热惩罚和与目标位置相关联的预期热水平，存储器结构中的多个物理位置的目标位置。

公开(公告)号：US20160077545A1

公开(公告)日：2016-03-17

申请号：US14489130

申请日：2014-09-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Wayne P. Burleson ,  Manish Arora ,  Indrani Paul ,  Yasuko Eckert

IPC: G06F1/08 ,  G06F1/26

CPC classification number: G06F1/12 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.

Abstract translation: 处理装置包括在第一定时域中的产生处理器单元和与第一定时域异步的第二定时域中的消耗处理器单元。 队列用于在生成处理器单元和消费处理器单元之间传送数据。 系统管理单元基于队列的丰满度的变化率来修改生成处理器单元或消费处理器单元中的一个或两个的操作频率或工作电压中的一个或两个。

公开(公告)号：US09251081B2

公开(公告)日：2016-02-02

申请号：US13957105

申请日：2013-08-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai K. Chang ,  Yasuko Eckert ,  Gabriel H. Loh ,  Lisa R. Hsu

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0848 ,  G06F12/122 ,  Y02D10/13

Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.

公开(公告)号：US09251069B2

公开(公告)日：2016-02-02

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US20140223445A1

公开(公告)日：2014-08-07

申请号：US13761985

申请日：2013-02-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。

公开(公告)号：US20140181413A1

公开(公告)日：2014-06-26

申请号：US13722808

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srilatha Manne ,  Michael Schulte ,  Lloyd Bircher ,  Madhu Saravana Sibi Govindan ,  Yasuko Eckert

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0806 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract translation: 提出了一种系统和方法。 一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为 处于修改状态。 通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度， 与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。