公开(公告)号：US10515884B2

公开(公告)日：2019-12-24

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

公开(公告)号：US10134683B2

公开(公告)日：2018-11-20

申请号：US15430355

申请日：2017-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  I-Cheng Wang ,  Wun-Jheng Syu ,  Yu-Tzu Peng

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/367 ,  H01L23/29 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

公开(公告)号：US09437532B2

公开(公告)日：2016-09-06

申请号：US14971165

申请日：2015-12-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H05K3/40 ,  H01L21/027 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

公开(公告)号：US09054118B2

公开(公告)日：2015-06-09

申请号：US14313046

申请日：2014-06-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Hsiang-Ming Feng ,  Bing-Yun Cheng

IPC: H01L21/56 ,  H01L23/34 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract translation: 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附接到基板。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。

公开(公告)号：US08866311B2

公开(公告)日：2014-10-21

申请号：US13624548

申请日：2012-09-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。

公开(公告)号：US10573624B2

公开(公告)日：2020-02-25

申请号：US16194265

申请日：2018-11-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  I-Cheng Wang ,  Wun-Jheng Syu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/24 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

公开(公告)号：US10332851B2

公开(公告)日：2019-06-25

申请号：US15630843

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Chieh Yang ,  Sheng-Ming Wang ,  Tien-Szu Chen

IPC: H01L23/00

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.

公开(公告)号：US10049893B2

公开(公告)日：2018-08-14

申请号：US15453656

申请日：2017-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Yu-Tzu Peng

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

公开(公告)号：US10002843B2

公开(公告)日：2018-06-19

申请号：US14667317

申请日：2015-03-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L23/31 ,  H05K3/20 ,  H01L23/00 ,  H05K1/11 ,  H05K3/10

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48245 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/1511 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/10 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

公开(公告)号：US09984989B2

公开(公告)日：2018-05-29

申请号：US14855849

申请日：2015-09-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.