公开(公告)号：US20240365551A1

公开(公告)日：2024-10-31

申请号：US18630142

申请日：2024-04-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Steven C. H. Hung ,  Hsueh Chung Chen ,  Naomi Yoshida ,  Sung-Kwan Kang ,  Balasubramanian Pranatharthiharan

IPC: H10B43/35 ,  H01L21/67 ,  H01L23/528 ,  H01L23/532 ,  H10B43/20

CPC classification number: H10B43/35 ,  H01L21/67161 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H10B43/20

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

公开(公告)号：US12100595B2

公开(公告)日：2024-09-24

申请号：US17347786

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Jianqiu Guo ,  Seshadri Ganguli ,  Steven C. H. Hung ,  Srinivas Gandikota

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545

Abstract: A sacrificial sealing layer is formed on a high-κ metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-κ metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-κ metal oxide layer to form a dipole region.

公开(公告)号：US12051734B2

公开(公告)日：2024-07-30

申请号：US18076958

申请日：2022-12-07

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Steven C. H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Yong Yang

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/517 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28568 ,  H01L29/518

Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

公开(公告)号：US11961734B2

公开(公告)日：2024-04-16

申请号：US17729643

申请日：2022-04-26

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang ,  Steven C. H. Hung

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L21/02247 ,  H01L21/02043 ,  H01L21/02274 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/67023 ,  H01L21/67207

Abstract: A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

公开(公告)号：US10431466B2

公开(公告)日：2019-10-01

申请号：US16159461

申请日：2018-10-12

Applicant: Applied Materials, Inc.

Inventor： Johanes S. Swenberg ,  Wei Liu ,  Houda Graoui ,  Steven C. H. Hung

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/02 ,  H01L21/324 ,  H01L21/321 ,  H01L21/285 ,  H01L29/45 ,  H01L21/768

Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.

公开(公告)号：US12230688B2

公开(公告)日：2025-02-18

申请号：US17667036

申请日：2022-02-08

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Srinivas Gandikota ,  Steven C. H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region.

公开(公告)号：US11996455B2

公开(公告)日：2024-05-28

申请号：US18130201

申请日：2023-04-03

Applicant: Applied Materials, Inc.

Inventor： Yongjing Lin ,  Karla M Bernal Ramos ,  Shih Chung Chen ,  Yixiong Yang ,  Lin Dong ,  Steven C. H. Hung ,  Srinivas Gandikota

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/02153 ,  H01L21/0228 ,  H01L21/28158 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7851

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

公开(公告)号：US11923441B2

公开(公告)日：2024-03-05

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6681 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/45536 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/6653

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11417517B2

公开(公告)日：2022-08-16

申请号：US16951858

申请日：2020-11-18

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang ,  Steven C. H. Hung

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67

Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.

公开(公告)号：US11289579B2

公开(公告)日：2022-03-29

申请号：US17034116

申请日：2020-09-28

Applicant: Applied Materials, Inc.

Inventor： Yongjing Lin ,  Karla M Bernal Ramos ,  Shih Chung Chen ,  Yixiong Yang ,  Lin Dong ,  Steven C. H. Hung ,  Srinivas Gandikota

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).