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公开(公告)号：US20150380354A1
公开(公告)日：2015-12-31
申请号：US14845435
申请日：2015-09-04
Inventor： Byoung-Gue MIN , Sang Choon KO , Jong-Won LIM , Hokyun AHN , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L23/535 , H01L23/48
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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公开(公告)号：US20150270822A1
公开(公告)日：2015-09-24
申请号：US14478295
申请日：2014-09-05
Inventor： Dong Min KANG , Seong Il KIM , Sang Heung LEE , Chull Won JU , Ho Kyun AHN , Hyung Sup YOON , Jong Won LIM
IPC: H03H7/38
CPC classification number: H03H7/38 , H01L23/642 , H01L2224/49175 , H01P1/2039 , H01P5/12 , H05K1/025 , H05K2201/09781
Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.
Abstract translation: 本文提供了一种包括匹配单元及其匹配方法的组件封装，所述匹配单元包括：衬底; 形成在所述基板上的传输线，所述传输线连接到所述部件封装的端子; 电连接所述传输线和中心部件的接合线; 以及具有通过布线连接与传输线电连接的多个电容器的电容器单元，其中匹配单元的电感通过调整接合线的长度而变化，并且匹配单元的电容可通过增加或减小而变化 通过延长或切断布线连接，在电容器单元内的电容器之间电连接到传输线的电容器的数量。
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13.发明申请FIELD-EFFECT TRANSISTOR FOR HIGH VOLTAGE DRIVING AND MANUFACTURING METHOD THEREOF 审中-公开用于高压驱动的场效应晶体管及其制造方法公开(公告)号：US20150194494A1
公开(公告)日：2015-07-09
申请号：US14243322
申请日：2014-04-02
Inventor： Ho Kyun AHN , Hae Cheon KIM , Zin Sig KIM , Sang Heung LEE , Byoung Gue MIN , Hyung Sup YOON , Dong Min KANG , Seong Il KIM , Jong Min LEE , Jong Won LIM , Yong Hwan KWON , Eun Soo NAM
IPC: H01L29/40 , H01L29/66 , H01L21/28 , H01L21/283 , H01L29/78 , H01L29/423
CPC classification number: H01L29/402 , H01L21/283 , H01L21/28593 , H01L29/2003 , H01L29/42312 , H01L29/42356 , H01L29/66462 , H01L29/66477 , H01L29/7787
Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.
Abstract translation: 公开了一种用于高电压驱动的场效应晶体管，其包括栅极电极结构，其中在漏极方向上延伸的栅极头由嵌入在栅极头的区域内的场板支撑以实现高电压驱动，以及 其制造方法。 因此，在漏极方向上延伸的栅极头通过使用绝缘层而被电隔离的场板支撑，使得可以稳定地制造包括延伸栅极头的栅电极，并且栅极电阻通过 栅极头在漏极的方向上延伸，栅极和漏极之间的电场峰值由包括在漏极方向上延伸的栅极和靠近栅极的场板的栅电极减小，由此实现 效果是器件的击穿电压增加。
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公开(公告)号：US20150144961A1
公开(公告)日：2015-05-28
申请号：US14175452
申请日：2014-02-07
Inventor： Hyung Sup YOON , Byoung Gue MIN , Ho Kyun AHN , Jong Won LIM , Dong Min KANG , Jong Min LEE
IPC: H01L29/778 , H01L29/45 , H01L29/66
CPC classification number: H01L29/42316 , H01L29/2003 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.
Abstract translation: 高频器件包括：形成在外延结构上的覆盖层; 源极和漏极形成在覆盖层上; 形成在所述源电极和漏电极以及所述覆盖层的整个表面上的阶梯形状的多层绝缘图案; 通过所述多层绝缘图案和所述覆盖层与所述外延结构接触的T形栅极; 以及在T形栅极和多层绝缘图案的整个表面上形成的钝化层。
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公开(公告)号：US20140103539A1
公开(公告)日：2014-04-17
申请号：US14021269
申请日：2013-09-09
Inventor： Byoung-Gue MIN , Sang Choon KO , Jong-Won Lim , Hokyun AHN , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L21/768 , H01L23/48 , H01L21/28 , H01L21/02
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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Patent Agency Ranking
公开(公告)号：US20190103483A1
公开(公告)日：2019-04-04
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun AHN , Min Jeong SHIN , Jeong Jin KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Hyung Seok LEE , Jong-Won LIM , Sungjae CHANG , Hyunwook JUNG , Kyu Jun CHO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE , Hong Gu JI
IPC: H01L29/78 , H01L29/20 , H01L29/45 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/3065
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US20190081166A1
公开(公告)日：2019-03-14
申请号：US16028612
申请日：2018-07-06
Inventor： Jae Won DO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Byoung-Gue MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jongmin LEE , Jong-Won LIM , Sungjae CHANG , Yoo Jin JANG , Hyunwook JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H01L29/778 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/205
Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.
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公开(公告)号：US20180145684A1
公开(公告)日：2018-05-24
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin CHANG , Jong-Won LIM , Dong Min KANG , Dong-Young KIM , Seong-il KIM , Hae Cheon KIM , Jae Won DO , BYOUNG-GUE MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , JONGMIN LEE , Sungjae CHANG , Yoo Jin JANG , HYUNWOOK JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353
CPC classification number: H03K17/687 , G11C5/14 , H03K3/353 , H03K17/08122 , H03K17/102 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/28 , H03K17/693 , H03K19/0175
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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公开(公告)号：US20170237171A1
公开(公告)日：2017-08-17
申请号：US15229891
申请日：2016-08-05
Inventor： Dong-Young KIM , Dong Min KANG , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Ho Kyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Yoo Jin JANG , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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20.发明申请SEMICONDUCTOR DEVICE HAVING STABLE GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权具有稳定的门结构的半导体器件及其制造方法公开(公告)号：US20150236108A1
公开(公告)日：2015-08-20
申请号：US14328247
申请日：2014-07-10
Inventor： Seong Il KIM , Dong Min KANG , Sang Heung LEE , Ho Kyun AHN , Hyung Sup YOON , Byoung Gue MIN , Jong Won LIM
IPC: H01L29/423 , H01L21/283 , H01L29/778
CPC classification number: H01L29/42312 , H01L21/28114 , H01L21/28587 , H01L21/28593 , H01L29/42316 , H01L29/66863 , H01L29/778 , H01L29/812
Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.
Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。
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