公开(公告)号：US06699752B2

公开(公告)日：2004-03-02

申请号：US10325260

申请日：2002-12-19

申请人： Er-Xuan Ping ,  Randhir Thakur

发明人： Er-Xuan Ping ,  Randhir Thakur

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  C23C16/24 ,  C23C16/56 ,  Y10S438/964

摘要： The present invention provides methods of forming in situ doped rugged silicon and semiconductor devices incorporating conductive rugged silicon. In one aspect, the methods involve forming a layer of amorphous silicon on a substrate at a substantially constant deposition temperature; and converting the layer of amorphous silicon into hemispherical grain silicon by subjecting the layer of amorphous silicon to substantially the deposition temperature while varying pressure.

摘要翻译： 本发明提供了形成原位掺杂的坚固硅和掺入导电坚固硅的半导体器件的方法。 在一个方面，所述方法包括在基本上恒定的沉积温度下在衬底上形成非晶硅层; 以及通过在改变压力的同时使非晶硅层基本上沉积温度来将非晶硅层转变成半球形晶粒硅。

公开(公告)号：US20150093907A1

公开(公告)日：2015-04-02

申请号：US14044138

申请日：2013-10-02

申请人： Ellie YIEH ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

发明人： Ellie YIEH ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

IPC分类号： H01L21/02 ,  H01L21/67

CPC分类号： H01L21/02271 ,  C23C14/021 ,  C23C14/046 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67017 ,  H01L21/67213 ,  H01L21/76224

摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.

摘要翻译： 实施例包括3D结构填充的方法和系统。 在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。 材料沉积在沟槽中。 材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。 在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。 该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

公开(公告)号：US08551855B2

公开(公告)日：2013-10-08

申请号：US12834942

申请日：2010-07-13

申请人： Huiwen Xu ,  Er-Xuan Ping ,  Xiying Costa

发明人： Huiwen Xu ,  Er-Xuan Ping ,  Xiying Costa

IPC分类号： H01L21/20

CPC分类号： H01L45/1675 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/3146 ,  H01L21/32139 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1683

摘要： Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.

摘要翻译： 提供了存储单元和形成这种存储单元的方法，其包括耦合到具有增加的电阻率的碳基可逆电阻率切换材料的转向元件和小于转向元件的最大电流能力的开关电流 用于控制通过碳基可逆电阻率开关材料的电流。 在具体实施例中，根据本发明的方法和装置形成具有第一宽度的转向元件，例如二极管，该第二宽度与第二宽度小于第一宽度的可逆电阻率开关材料（例如aC）耦合。

公开(公告)号：US08440567B2

公开(公告)日：2013-05-14

申请号：US13033268

申请日：2011-02-23

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/302

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20120193756A1

公开(公告)日：2012-08-02

申请号：US13020007

申请日：2011-02-02

申请人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

发明人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

IPC分类号： H01L29/861 ,  H01L21/36 ,  H01L29/92

CPC分类号： H01L27/1021 ,  H01L29/868 ,  Y10S438/90

摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。 提供了许多其他方面。

公开(公告)号：US08093123B2

公开(公告)日：2012-01-10

申请号：US12541075

申请日：2009-08-13

申请人： Huiwen Xu ,  Er-Xuan Ping

发明人： Huiwen Xu ,  Er-Xuan Ping

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1052

摘要： Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the pillar to form multiple memory cells. Memory cells formed from such methods, as well as numerous other aspects are also disclosed.

摘要翻译： 公开了形成存储器单元的方法，其包括在衬底上形成柱，所述柱包括转向元件和存储元件，并且通过柱垂直地执行一个或多个蚀刻以形成多个存储单元。 还公开了由这些方法形成的存储单元以及许多其它方面。

公开(公告)号：US20100282164A1

公开(公告)日：2010-11-11

申请号：US12840153

申请日：2010-07-20

申请人： Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

发明人： Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

IPC分类号： C23C16/00 ,  B05C11/00

CPC分类号： C23C16/00 ,  C23C16/46

摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

摘要翻译： 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US20090257265A1

公开(公告)日：2009-10-15

申请号：US12153872

申请日：2008-05-27

申请人： Xiying Chen ,  Bing K. Yen ,  Dat Nguyen ,  Huiwen Xu ,  George Samachisa ,  Tanmay Kumar ,  Er-Xuan Ping

发明人： Xiying Chen ,  Bing K. Yen ,  Dat Nguyen ,  Huiwen Xu ,  George Samachisa ,  Tanmay Kumar ,  Er-Xuan Ping

IPC分类号： G11C11/00 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/009 ,  G11C2213/35 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1675

摘要： A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.

摘要翻译： 非易失性存储单元包括与存储元件串联定位的转向元件。 存储元件包括碳材料，并且存储单元包括具有多个存储器级别的可重写单元。

公开(公告)号：US07422635B2

公开(公告)日：2008-09-09

申请号：US10652461

申请日：2003-08-28

申请人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  David J. Kubista ,  Cem Basceri

发明人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  David J. Kubista ,  Cem Basceri

IPC分类号： C23C16/00 ,  C23C16/455 ,  H01L21/306

CPC分类号： C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

摘要： The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

摘要翻译： 本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。 一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。 第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。 第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。 第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。 第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

公开(公告)号：US07279398B2

公开(公告)日：2007-10-09

申请号：US11327794

申请日：2006-01-06

申请人： Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

发明人： Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/302 ,  H01L21/461 ,  H01L21/469

CPC分类号： C23C16/45527 ,  C23C16/34 ,  C23C16/45546

摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

摘要翻译： 本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。 一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。 当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。 第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。 在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。 此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。