公开(公告)号：US20160358922A1

公开(公告)日：2016-12-08

申请号：US14729845

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/18 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

Abstract translation: 提供一种形成半导体结构的方法，其包括具有第一锗含量的压缩应变硅锗合金翅片和具有小于第一锗含量的第二锗含量的拉伸应变硅锗合金翅片。 不同的应变和锗含量的硅锗合金翅片位于同一基板上。 该方法包括在一组硅锗合金翅片周围形成硅包覆层，并且在另一组硅锗合金翅片周围形成含锗材料包层。 然后使用热混合形成不同的应变和锗含量的硅锗合金翅片。

公开(公告)号：US09484430B2

公开(公告)日：2016-11-01

申请号：US14720328

申请日：2015-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wilfried E. Haensch ,  Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L29/40 ,  H01L29/417 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78621

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

公开(公告)号：US09484359B2

公开(公告)日：2016-11-01

申请号：US14696736

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B Doris ,  Pranita Kerber ,  Ali Khakifirooz

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

Abstract: An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

公开(公告)号：US09472446B2

公开(公告)日：2016-10-18

申请号：US14307902

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1029 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.

Abstract translation: 所公开的一种方法包括形成具有阶梯状横截面轮廓的整体翅片结构，翅片结构具有位于上部下方的上部和下部，其中上部具有第一宽度和下部 部分具有小于第一宽度的第二宽度，在邻近整个翅片结构的沟槽中形成绝缘材料层，使得整个翅片结构的上部和整个翅片结构的下部的一部分暴露 在绝缘材料层的上表面之上，并且围绕整个翅片结构的暴露的上部和整个翅片结构的下部的暴露部分形成栅极结构。

公开(公告)号：US09455331B1

公开(公告)日：2016-09-27

申请号：US14796646

申请日：2015-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8236 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.

Abstract translation: 一种形成包括形成多个半导体柱的半导体器件的方法。 在至少一组相邻的半导体柱之间形成介电间隔物。 半导体材料外延地形成在相邻半导体柱的侧壁上，其中电介质间隔物阻挡形成在第一半导体柱上的外延半导体材料的第一部分与形成在第二半导体柱上的第二部分外延半导体材料合并。

公开(公告)号：US09385023B1

公开(公告)日：2016-07-05

申请号：US14712462

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joel P. de Souza ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L21/70 ,  H01L21/762 ,  H01L21/225 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/76245 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height that is located on a first buried oxide structure. The structure further includes a second silicon fin of a second height that is located on a second buried oxide structure that is spaced apart from the first buried oxide structure. The second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar of a topmost surface with the second silicon fin.

Abstract translation: 提供了包含具有不同高度的硅散热片的半导体结构，同时为了工艺可行性而保持合理的翅片高宽比。 半导体结构包括位于第一掩埋氧化物结构上的第一高度的第一硅鳍。 该结构还包括第二高度的第二硅片，其位于与第一掩埋氧化物结构间隔开的第二掩埋氧化物结构上。 第二硅片的第二高度大于第一硅片的第一高度，但是第一硅片的最顶面与第二硅片的最顶面共面。

公开(公告)号：US09379135B2

公开(公告)日：2016-06-28

申请号：US14723681

申请日：2015-05-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/76205 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.

公开(公告)号：US20160181095A1

公开(公告)日：2016-06-23

申请号：US14574533

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kanggou Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02587 ,  H01L21/02612 ,  H01L21/02664 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/66795

Abstract: Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon layer on top of a BOX. At least one fin upon a thin layer of silicon and a hard mask layer over the at least one fin is formed using the silicon layer on top of the BOX. A SiGe layer is epitaxially grown from exposed portions of the fin and the thin layer of silicon. Spacers are formed on sidewalls of the hard mask. Regions of the SiGe layer and the thin layer of silicon not protected by the spacers are etched, such that portions of the BOX are exposed. A condensation process converts the fin to SiGe and to convert the SiGe layer to oxide. The hard mask, the spacers, and the oxide layer are removed.

Abstract translation: 本发明的实施例包括制造SiGe鳍片的方法和所得到的结构。 提供SOI衬底，其至少包括在BOX顶部的硅层。 使用BOX顶部的硅层，在至少一个散热片上的薄层硅层和硬掩模层上形成至少一个鳍片。 SiGe层从翅片和薄层硅的暴露部分外延生长。 垫片形成在硬掩模的侧壁上。 SiGe层的区域和未被间隔物保护的硅的薄层被蚀刻，使得BOX的部分被暴露。 冷凝过程将翅片转换成SiGe并将SiGe层转化为氧化物。 去除硬掩模，间隔物和氧化物层。

公开(公告)号：US20160163879A1

公开(公告)日：2016-06-09

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种半导体器件。 半导体器件可以包括设置在衬底上的第一介电层; 设置在所述第一电介质层上的一组偏置线; 第二电介质层，设置在所述第一电介质层上和所述一组偏置线之间，其中所述第二电介质层的厚度小于所述第一介电层的厚度; 设置在所述第二电介质层的部分上的图案化半导体层; 以及设置在所述偏置线组之上的图案化半导体层上的一组器件。

公开(公告)号：US09349835B2

公开(公告)日：2016-05-24

申请号：US14027720

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan Veera Venkata Satya Surisetty

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41766 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

Abstract translation: 半导体器件包括栅极和低k间隔物。 低k间隔物包括形成在栅极侧壁上的低k隔离部分和形成在与栅极相邻的下面基底的顶表面上的低k隔离部分。 当结构先前已经进行了栅极处理制造阶段时，可以暴露栅极和衬底顶表面的至少一部分，从而允许形成低k间隔物。 该曝光可以包括去除任何原始的栅极间隔物，去除形成在原始间隔物上的原始衬垫，以及去除在衬垫上形成的任何原始填充材料。