公开(公告)号：US10049942B2

公开(公告)日：2018-08-14

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/265 ,  H01L21/266 ,  H01L29/167 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

公开(公告)号：US09991167B2

公开(公告)日：2018-06-05

申请号：US15085077

申请日：2016-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US20170179257A1

公开(公告)日：2017-06-22

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US09660105B2

公开(公告)日：2017-05-23

申请号：US15089647

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L27/12 ,  H01L27/115 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

公开(公告)号：US09450072B2

公开(公告)日：2016-09-20

申请号：US14519615

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L21/027 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L29/66545 ,  H01L21/02107 ,  H01L21/28132 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

Abstract translation: 在形成跨越至少一个半导体材料部分的栅极腔形成之后，在栅极介电层上形成栅极电介质层和至少一个功函数材料层。 图案化至少一个功函数材料层和栅介电层，使得至少一个功函数材料层的剩余部分仅存在于至少一个半导体材料部分附近。 具有比至少一个功函数材料层更大的导电性的导电材料沉积在栅极腔的剩余部分中。 替代栅极结构中的导电材料部分在去除了至少一个功函数材料层和栅极电介质层的区域中具有替换栅极结构的全宽。

公开(公告)号：US09305930B2

公开(公告)日：2016-04-05

申请号：US14102843

申请日：2013-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L27/12 ,  H01L21/336

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

Abstract translation: 提供了一种双鳍单浮栅配置的闪存器件。 半导体翅片形成在背栅导体层和背栅电介质层的堆叠上。 在阵列环境中形成一对半导体散热片，使得能够沿阵列内的半导体鳍片的长度方向形成浅沟槽隔离结构。 在半导体鳍片的侧壁上形成隧道电介质之后，通过沉积保形导电材料层和各向同性蚀刻，在每对靠近近端的半导体鳍片之间形成浮栅电极。 通过介电层和导电材料层的沉积和图案化来形成控制栅极电介质和控制栅电极。

公开(公告)号：US09627480B2

公开(公告)日：2017-04-18

申请号：US14315385

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20170076991A1

公开(公告)日：2017-03-16

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L21/823814 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7848

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

Abstract translation: 本公开的一个方面提供了一种不对称半导体器件。 不对称半导体器件可以包括：衬底; 以及设置在所述衬底上的鳍状场效应晶体管（FINFET），所述FINFET包括：设置在栅极附近的一组翅片; 第一外延区域，设置在所述一组鳍片上的源极区域上，所述第一外延区域具有第一高度; 以及设置在所述散热片组上的漏极区域上的第二外延区域，所述第二外延区域具有第二高度，其中所述第一高度与所述第二高度不同。

公开(公告)号：US09548356B2

公开(公告)日：2017-01-17

申请号：US14714779

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kerber ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。