公开(公告)号：US20170301551A1

公开(公告)日：2017-10-19

申请号：US15099641

申请日：2016-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Donghun KANG ,  Balaji KANNAN ,  Jinping LIU

IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/092 ,  H01L21/285

CPC classification number: H01L21/3085 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: A method of fabricating multi Vth devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second regions; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

公开(公告)号：US20170033224A1

公开(公告)日：2017-02-02

申请号：US14812653

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Zhenyu HU ,  Hong YU ,  Jinping LIU

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/7853 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66795

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract translation: 一种方法可以包括执行蚀刻工艺以限定具有第一深度的翅片沟槽，第一深度小于翅片的目标高度。 方法还可以包括形成层以保护限定翅片沟槽的侧壁。 方法还可以包括执行第二蚀刻工艺以增加散热片沟槽的深度。

公开(公告)号：US20150123146A1

公开(公告)日：2015-05-07

申请号：US14071170

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat KRISHNAN ,  Jody A. FRONHEISER ,  Jinping LIU ,  Bongki LEE

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。

公开(公告)号：US20200020769A1

公开(公告)日：2020-01-16

申请号：US16032878

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei PENG ,  Sang Woo LIM ,  Matthew Wahlquist STOKER ,  Huang LIU ,  Jinping LIU

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3x fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3x fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

公开(公告)号：US20180233404A1

公开(公告)日：2018-08-16

申请号：US15430039

申请日：2017-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui SHU ,  Byoung Youp KIM ,  Jinping LIU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to variable space mandrel cut for self-aligned double patterning and methods of manufacture. The method includes: forming a plurality of mandrels on a substrate; forming spacers about the plurality of mandrels and exposed portions of the substrate; removing a portion of at least one of the plurality of mandrels to form an opening; and filling in the opening with material.

公开(公告)号：US20180019313A1

公开(公告)日：2018-01-18

申请号：US15718958

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC: H01L29/47 ,  H01L21/285 ,  H01L21/8238 ,  H01L21/266 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface of the n-FET region source/drain regions; and titanium silicide (TiSi) forming an upper surface of the p-FET region source/drain regions.

公开(公告)号：US20170338156A1

公开(公告)日：2017-11-23

申请号：US15156767

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI ,  Jinping LIU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

公开(公告)号：US20160005657A1

公开(公告)日：2016-01-07

申请号：US14853537

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat KRISHNAN ,  Jody A. FRONHEISER ,  Jinping LIU ,  Bongki LEE

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxial material is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxial material on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延材料在增加的（100）区域上生长。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长另外的外延材料的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并， 同时也增加了他们的数量。

公开(公告)号：US20150255353A1

公开(公告)日：2015-09-10

申请号：US14197267

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Jinping LIU ,  Xiang HU ,  Dae-han CHOI ,  Dae Geun YANG ,  Churamani GAIRE ,  Akshey SEHGAL

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L27/0924

Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.

Abstract translation: 公开了用单个掩模版形成FinFET源极/漏极区域的方法以及所得到的器件。 实施例可以包括在衬底上形成第一鳍片和第二鳍片，形成跨越第一鳍片和第二鳍片的栅极，在栅极的两侧去除第一鳍片和第二鳍片的部分，在第二鳍片上形成硅磷顶部 第一鳍片和第二鳍片代替部分，去除第一鳍片上的磷磷顶部，并且在第一鳍片上形成硅锗顶部代替硅磷顶部。