公开(公告)号：US20150270159A1

公开(公告)日：2015-09-24

申请号：US14220260

申请日：2014-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Hongliang SHEN ,  Huang LIU ,  Tao HAN ,  Xiang HU

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/76229 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111

Abstract: Semiconductor structure fabrication methods are provided which include: forming one or more trenches and a plurality of plateaus within a substrate structure; providing a conformal stop layer over the substrate structure, including over the plurality of plateaus, the conformal stop layer being or including oxidized polycrystalline silicon; depositing a material over the substrate structure to fill the one or more trenches and cover the plurality of plateaus thereof; and planarizing the material using a slurry to form coplanar surfaces of the material and the conformal stop layer, wherein the slurry reacts with the oxidized polycrystalline silicon of the conformal stop layer to facilitate providing the coplanar surfaces with minimal dishing of the material. Various embodiments are provided, including different methods of providing the conformal stop layer, such as by oxidizing at least an upper portion of polycrystalline silicon, or by performing an in-situ steam growth process.

Abstract translation: 提供半导体结构制造方法，其包括：在衬底结构内形成一个或多个沟槽和多个平台; 在所述衬底结构上提供保形停止层，包括在所述多个平台上，所述共形停止层包括氧化的多晶硅; 在衬底结构上沉积材料以填充所述一个或多个沟槽并覆盖其多个平台; 并且使用浆料平坦化材料以形成材料和共形停止层的共面表面，其中浆料与保形停止层的氧化多晶硅反应，以便于提供最小的凹陷的共面表面。 提供了各种实施例，包括提供保形停止层的不同方法，例如通过氧化至少多晶硅的上部，或者通过进行原位蒸汽生长过程。

公开(公告)号：US20150017803A1

公开(公告)日：2015-01-15

申请号：US13939322

申请日：2013-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Xiang HU ,  Paul ACKMANN ,  Sarasvathi THANGARAJU

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

Abstract translation: 通过（TSV）结构制造贯穿衬底通过以下方式促进：在衬底内形成至少一个应力缓冲液; 通过所述衬底内的接触形成贯通衬底，其中所述贯通衬底通孔结构和所述应力缓冲器被设置为彼此相邻或接触; 并且其中所述应力缓冲器包括配置或者被布置在相对于所述贯通基板通孔导体的位置处，至少部分地根据所述TSV结构是否是隔离的TSV结构，链接的TSV结构或 至少部分地基于TSV结构的类型来定义通过基于导体的贯穿衬底的应力缓冲器的应力缓解。

公开(公告)号：US20180226294A1

公开(公告)日：2018-08-09

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David Michael PERMANA ,  Guillaume BOUCHE ,  Andy WEI ,  Mark ZALESKI ,  Anbu Selvam KM MAHALINGAM ,  Craig Michael CHILD, JR. ,  Roderick Alan AUGUR ,  Shyam PAL ,  Linus JANG ,  Xiang HU ,  Akshey SEHGAL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170061044A1

公开(公告)日：2017-03-02

申请号：US14841037

申请日：2015-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guo Xiang NING ,  Yuping REN ,  David POWER ,  Lalit SHOKEEN ,  Chin Teong LIM ,  Paul W. ACKMANN ,  Xiang HU

IPC: G06F17/50 ,  G03F1/36 ,  G05B15/02

CPC classification number: G06F17/5009 ,  G03F1/36 ,  G06F17/5081

Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

Abstract translation: 提供了用于产生用于OPC或MPC工艺流程的最终电介质蚀刻补偿表和最终硬掩模蚀刻补偿表的方法和装置。 实施例包括在晶片上执行重叠图案分类; 基于图案分类来校准电介质蚀刻偏压或硬掩模蚀刻偏压; 将通孔层与金属层的CD重叠与通孔层的CD重叠与金属层的下连接金属层或CD重叠与上连接通孔层和金属层的CD重叠与 通过层反对标准; 将最终介电蚀刻补偿和硬掩模蚀刻补偿表输出到OPC或MPC工艺流程; 并重复校准，比较和输出剩余的通孔层或金属层的步骤。

公开(公告)号：US20160099171A1

公开(公告)日：2016-04-07

申请号：US14969154

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Yuping REN ,  Duohui BEI ,  Sipeng GU ,  Huang LIU

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

公开(公告)号：US20150198435A1

公开(公告)日：2015-07-16

申请号：US14155504

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alok VAID ,  Abner BELLO ,  Sipeng GU ,  Lokesh SUBRAMANY ,  Xiang HU ,  Akshey SEHGAL

IPC: G01B11/06 ,  H01L21/66

CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。

公开(公告)号：US20150132962A1

公开(公告)日：2015-05-14

申请号：US14076386

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Dae-Han CHOI ,  Dae Geun YANG ,  Taejoon HAN ,  Andy WEI

IPC: H01L21/308

CPC classification number: H01L21/0337

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract translation: 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US20150076111A1

公开(公告)日：2015-03-19

申请号：US14031563

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Gabriel PADRON WELLS ,  Jack Chao-Hsu CHANG ,  Mingmei WANG ,  Taejoon HAN

IPC: H01J37/32

CPC classification number: H01J37/32146 ,  H01J37/32174 ,  H01J2237/3341 ,  H01J2237/3348 ,  H01L21/3065 ,  H01L21/32137

Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.

Abstract translation: 通过改变对蚀刻系统的射频（RF）功率脉冲的供应，便于蚀刻系统蚀刻结构的特征。 变化通过至少一个特征提供所提供的RF功率脉冲中提供的RF功率脉冲的至少一个RF功率脉冲，其偏离所提供的RF功率脉冲的一个或多个其它RF功率脉冲。