公开(公告)号：US09892970B2

公开(公告)日：2018-02-13

申请号：US15171314

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/498 ,  H01L21/3065

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

公开(公告)号：US20170365775A1

公开(公告)日：2017-12-21

申请号：US15690828

申请日：2017-08-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  H01L41/25 ,  G06F17/50 ,  H01L21/768 ,  H01L23/00 ,  H01L41/08 ,  H03H9/64 ,  H01L23/48 ,  H01L27/06 ,  H01L25/16 ,  H01L23/66 ,  H01L49/02

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

公开(公告)号：US20170352592A1

公开(公告)日：2017-12-07

申请号：US15171314

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/311 ,  H01L49/02 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

公开(公告)号：US09831194B1

公开(公告)日：2017-11-28

申请号：US15203326

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tom C. Lee ,  Cathryn J. Christiansen ,  Ian A. McCallum-Cook ,  Anthony K. Stamper

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L23/585 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated with the portion of the substrate, an interconnect structure on the active circuit region, and a crackstop extending through the interconnect structure. A groove extends through the interconnect structure to the substrate at a location exterior of the crackstop. A stress-containing layer is formed on at least a portion of the groove.

公开(公告)号：US20170323855A1

公开(公告)日：2017-11-09

申请号：US15594059

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Edward C. Cooney, III ,  Laurie M. Krywanczyk

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76819 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493

Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

公开(公告)号：US09728509B1

公开(公告)日：2017-08-08

申请号：US15147525

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Edward C. Cooney, III ,  Laurie M. Krywanczyk

IPC: H01L23/544 ,  H01L23/528 ,  H01L23/58 ,  H01L21/768 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/304 ,  H01L23/532

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/768 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493

Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

公开(公告)号：US20170221831A1

公开(公告)日：2017-08-03

申请号：US15014759

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US20170186643A1

公开(公告)日：2017-06-29

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US20160372396A1

公开(公告)日：2016-12-22

申请号：US14745800

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L23/367 ,  H01L21/48 ,  H01L29/08 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L23/367 ,  H01L21/4882 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/732

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Abstract translation: 芯片封装和形成芯片封装的方法。 芯片封装包括功率放大器和构造成影响热能传输的热通路结构。 功率放大器包括第一发射器指状物和第二发射器指状物，其具有至少一个基于与热路径结构接近度选择的参数。

公开(公告)号：US09252080B1

公开(公告)日：2016-02-02

申请号：US14514640

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L21/24 ,  H01L23/48 ,  H01L21/768 ,  H01L21/321

CPC classification number: H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Abstract translation: 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。