公开(公告)号：US20220102483A1

公开(公告)日：2022-03-31

申请号：US17033279

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Kaan Oguz ,  Neelam Prabhu Gaunkar ,  Aleksandar Aleksov ,  Henning Braunisch ,  I-Cheng Tung

IPC: H01L49/02

Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20250006791A1

公开(公告)日：2025-01-02

申请号：US18346227

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dominique A. Adams ,  Gauri Auluck ,  Pratyush P. Buragohain ,  Scott B. Clendenning ,  Punyashloka Debashis ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

公开(公告)号：US20240373644A1

公开(公告)日：2024-11-07

申请号：US18778857

申请日：2024-07-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H10B53/00 ,  G11C11/22 ,  H01G4/008 ,  H01L27/08 ,  H10B53/10

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

Abstract: A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/65 ,  H01L28/75 ,  H01L27/10829

Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US20210408018A1

公开(公告)日：2021-12-30

申请号：US16914140

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H01L27/11502 ,  H01L49/02 ,  H01L27/08 ,  H01G4/008 ,  G11C11/22

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US12224309B2

公开(公告)日：2025-02-11

申请号：US17116315

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Kaan Oguz ,  I-Cheng Tung ,  Uygar E. Avci ,  Matthew V. Metz ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Arnab Sen Gupta

IPC: H01L23/522 ,  H01L49/02

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

公开(公告)号：US12100731B2

公开(公告)日：2024-09-24

申请号：US16914161

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Matthew Metz ,  Uygar Avci

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L27/0629 ,  H01L28/55

Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.