公开(公告)号：US20200287036A1

公开(公告)日：2020-09-10

申请号：US16645758

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/205 ,  H01L29/15 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200161473A1

公开(公告)日：2020-05-21

申请号：US16633094

申请日：2017-09-17

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Willy RACHMADY ,  Brian S. DOYLE ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

公开(公告)号：US20200066843A1

公开(公告)日：2020-02-27

申请号：US16612259

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Cheng-Ying HUANG ,  Harold W. KENNEL ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

公开(公告)号：US20200006492A1

公开(公告)日：2020-01-02

申请号：US16022510

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20190189770A1

公开(公告)日：2019-06-20

申请号：US16284980

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Jack T. KAVALIEROS ,  Sanaz K. GARDNER

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/08

CPC classification number: H01L29/6681 ,  B82Y10/00 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/30612 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20190122972A1

公开(公告)日：2019-04-25

申请号：US16094817

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Willy RACHMADY ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L23/498 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.

公开(公告)号：US20190035897A1

公开(公告)日：2019-01-31

申请号：US16072313

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Will RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Matthew V. METZ ,  Sean T. MA

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

公开(公告)号：US20180204842A1

公开(公告)日：2018-07-19

申请号：US15574092

申请日：2015-06-23

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Niloy MUKHERJEE ,  Rafael RIOS ,  Prashant MAJHI ,  Van H. LE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Gilbert DEWEY ,  Marko RADOSAVLJEVIC

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/786 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/108 ,  G11C13/0007 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/7869 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.

公开(公告)号：US20180158737A1

公开(公告)日：2018-06-07

申请号：US15576248

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Karthik JAMBUNATHAN

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.

公开(公告)号：US20170256408A1

公开(公告)日：2017-09-07

申请号：US15604550

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz K. GARDNER ,  Pragyansri PATHI ,  Matthew V. METZ ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  James M. POWERS ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: G06Q30/02

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.