公开(公告)号：US20170250145A1

公开(公告)日：2017-08-31

申请号：US15595581

申请日：2017-05-15

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D. Heppner ,  Mitul B. Modi ,  Anna M. Prakash

IPC: H01L23/60 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US20170166407A1

公开(公告)日：2017-06-15

申请号：US14969707

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Pramod Malatkar ,  Joshua D. Heppner ,  Jimin Yao

IPC: B65G47/91 ,  H05K13/04 ,  B25J15/06

CPC classification number: B65G47/91 ,  B25J15/0061 ,  B25J15/0616 ,  B65G47/918 ,  H05K13/0409 ,  H05K13/041

Abstract: A pick and place machine includes a frame to adjustably mount, in three dimensions, a plurality of vacuum nozzles over a component to be picked according to a first embodiment a multi-head PnP mechanism may be simple and flexible to train for a wide variety of component and package shapes and sizes. Multiple PnP nozzles are staggered independently in three axes. According to a second embodiment, a PnP mechanism uses an array of self-learning nozzles that adapt by adjusting the z height of individual nozzles to the shape of the object to be picked.

公开(公告)号：US09385444B2

公开(公告)日：2016-07-05

申请号：US14132924

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Vijaykumar Krithivasan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley

IPC: H01R4/50 ,  H01R13/447 ,  H05K1/18 ,  H01R12/71

CPC classification number: H01R4/5066 ,  H01R12/714 ,  H01R13/447 ,  H05K1/181 ,  H05K2201/10325 ,  H05K2201/10719 ,  Y10T29/49204

Abstract: An apparatus comprises a socket for an integrated circuited (IC), wherein the socket includes a socket body that includes a plurality of land grid array contacts for contacting the IC, an alignment mechanism, and a locking mechanism, and a cover for the socket, wherein the cover is vertically alignable with the alignment mechanism of the socket body and laterally slidable over the grid array contacts upon alignment to engage the locking mechanism of the socket body.

Abstract translation: 一种装置包括用于集成电路（IC）的插座，其中插座包括插座主体，其包括用于接触IC的多个平台格栅阵列触点，对准机构和锁定机构以及用于插座的盖， 其中所述盖子与所述插座主体的对准机构垂直对准，并且在对准时可横向滑动在所述格栅阵列上方，以接合所述插座主体的锁定机构。

公开(公告)号：US11653467B2

公开(公告)日：2023-05-16

申请号：US17251697

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chris D. Lucero ,  Khine Han ,  Joshua D. Heppner ,  Christopher Rossi ,  Hadi Sharifi ,  Aniekeme Udofia ,  Abdul Bailey ,  Katherine Perkins ,  Kevin Lowell Hudson ,  Roderick E. Kronschnabel ,  Neha Purushothaman

IPC: H05K7/14 ,  G06F15/78 ,  H05K1/14

CPC classification number: H05K7/1422 ,  G06F15/7803 ,  H05K1/141

Abstract: An Internet of Things (IoT) apparatus including a plurality of boards and one or more connectors to couple IoT modules to one or more of the plurality of boards and to couple the plurality of boards to each other. The connectors include stacking connectors on both sides of at least some of the boards and at least some of the IoT modules to be coupled to the boards.

公开(公告)号：US20190281717A1

公开(公告)日：2019-09-12

申请号：US16335050

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Son V. Nguyen ,  Rajat Goyal ,  David B. Lampner ,  Dilan Seneviratne ,  Albert S. Lopez ,  Joshua D. Heppner ,  Srinivas V. Pietambaram ,  Shawna M. Liff ,  Nadine L. Dabby

IPC: H05K5/06 ,  H05K5/00 ,  H05K5/02

Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.

公开(公告)号：US10205292B2

公开(公告)日：2019-02-12

申请号：US15716356

申请日：2017-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R33/76 ,  H01L23/32 ,  H01L23/498

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20180226358A1

公开(公告)日：2018-08-09

申请号：US15945023

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US09824901B2

公开(公告)日：2017-11-21

申请号：US15085538

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Adel A. Elsherbini ,  Joshua D. Heppner ,  Shawna M. Liff

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L23/315 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/467 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.

公开(公告)号：US20170266948A1

公开(公告)日：2017-09-21

申请号：US15072285

申请日：2016-03-16

Applicant: Intel Corporation

Inventor： Joshua D. Heppner ,  Shawna M. Liff ,  Eric J. Li ,  Anna M. Prakash

IPC: B41F15/18 ,  B41F15/44

CPC classification number: B41F15/18 ,  B41F15/12 ,  B41F15/44 ,  B41L13/02 ,  B41L13/12 ,  B41L13/14 ,  H05K3/1233

Abstract: Described is an apparatus which comprises: a squeegee head which is operable to drop a material; and a vacuum manifold attachable to the squeegee head, wherein the vacuum manifold is operable to create a vacuum in a space prior to the squeegee head is to drop the material.

公开(公告)号：US09728425B1

公开(公告)日：2017-08-08

申请号：US15089491

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： Joshua D. Heppner ,  Serge Roux ,  Michael J. Baker ,  Javier A. Falcon

IPC: H01L21/56 ,  H01L21/67 ,  B29C35/08 ,  B29C70/84 ,  B29C70/80 ,  B29C70/88 ,  H01L23/31 ,  B29K63/00 ,  B29L31/34

CPC classification number: H01L21/563 ,  B29K2063/00 ,  B29K2995/0005 ,  B29L2031/3481 ,  H01L21/67126 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/92125

Abstract: Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.