公开(公告)号：US11119835B2

公开(公告)日：2021-09-14

申请号：US15859365

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Evan Custodio ,  Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel

IPC: G06F9/54 ,  G02B6/44 ,  G06F15/78 ,  H03K19/0175

Abstract: Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.

公开(公告)号：US11115497B2

公开(公告)日：2021-09-07

申请号：US16829814

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Slawomir Putyrski ,  Susanne M. Balle ,  Thomas Willhalm ,  Karthik Kumar

IPC: H04L29/08 ,  H04L12/911

Abstract: Technologies for providing advanced resource management in a disaggregated environment include a compute device. The compute device includes circuitry to obtain a workload to be executed by a set of resources in a disaggregated system, query a sled in the disaggregated system to identify an estimated time to complete execution of a portion of the workload to be accelerated using a kernel, and assign, in response to a determination that the estimated time to complete execution of the portion of the workload satisfies a target quality of service associated with the workload, the portion of the workload to the sled for acceleration.

公开(公告)号：US10686688B2

公开(公告)日：2020-06-16

申请号：US15655846

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  John Chun Kwok Leung ,  Suraj Prabhakaran ,  Murugasamy K. Nachimuthu ,  Slawomir Putyrski

IPC: H04L12/26 ,  G06F16/22 ,  G06F16/23 ,  H04L12/24 ,  H04L12/927 ,  H04Q9/00 ,  H04L29/08 ,  H04L12/925

Abstract: Techniques for reducing fragmentation in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to receive a dynamic tolerated fragmentation for the one or more remote resources. The compute node may be configured to monitor the performance of the one or more remote resources. For example, the compute node may be configured to monitor if one or more of the monitored resources were to exceed a threshold bandwidth or latency range as defined by the dynamic tolerated fragmentation. The compute node may be configured to determine that the monitored performance of the one or more remote resources is outside a threshold defined by the dynamic tolerated fragmentation. If one or more of the remote resources is outside the threshold, for a predetermined period of time, or otherwise, the compute node may be configured to determine so and take appropriate measures, such as generating a message indicating that performance of the one or more remote resources is outside a threshold defined by the dynamic tolerated fragmentation. Other embodiments are described and claimed.

公开(公告)号：US10437731B2

公开(公告)日：2019-10-08

申请号：US14998070

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Slawomir Putyrski

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/123

Abstract: In embodiments, apparatuses, methods and storage media associated with a multi-level cache are described. A first storage level may receive an input/output (I/O) request from a second storage level of the multi-level cache, wherein the I/O request is associated with a data. The first storage level may further receive an indicator to indicate whether the data is stored or will be stored in the second storage level. The first storage level may determine whether to store the data in the first storage level based on the indicator. Other embodiments may be described and/or claimed.

公开(公告)号：US20170255494A1

公开(公告)日：2017-09-07

申请号：US15112309

申请日：2015-02-23

Applicant: Intel Corporation

Inventor： Katalin K. Bartfai-Walcott ,  John Kennedy ,  Thijs Metsch ,  Chris Woods ,  Giovani Estrada ,  Alexander Leckey ,  Joseph Butler ,  Slawomir Putyrski

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  H04L41/0803 ,  H04L41/082 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12

Abstract: Examples are described for computing resource discovery and management for a system of configurable computing resources that may include disaggregate physical elements such as central processing units, storage devices, memory devices, network input/output devices or network switches. In some examples, these disaggregate physical elements may be located within one or more racks of a data center.

公开(公告)号：US12288101B2

公开(公告)日：2025-04-29

申请号：US18405679

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F15/80 ,  G06F3/06 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F16/174 ,  G06F21/57 ,  G06F21/62 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  H01R13/453 ,  H01R13/631 ,  H03K19/173 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L9/08 ,  H04L12/28 ,  H04L12/46 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/14 ,  G06F11/14 ,  G06F16/28 ,  H04L9/40 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L47/78 ,  H04Q11/00

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US11907557B2

公开(公告)日：2024-02-20

申请号：US17681025

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F15/80 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  G06F9/455 ,  H05K7/14 ,  H04L61/5007 ,  H04L67/63 ,  H04L67/75 ,  H03M7/30 ,  H03M7/40 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L41/044 ,  H04L49/104 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H04L47/78 ,  G06F16/28 ,  H04Q11/00 ,  G06F11/14 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L9/40

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0653 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/45533 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5005 ,  G06F9/505 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/5083 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/079 ,  G06F11/0751 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3079 ,  G06F11/3409 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/453 ,  H01R13/4536 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/1452 ,  H05K7/1487 ,  H05K7/1491 ,  G06F11/1453 ,  G06F12/023 ,  G06F15/80 ,  G06F16/285 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L47/78 ,  H04L63/1425 ,  H04Q11/0005 ,  H05K7/1447 ,  H05K7/1492

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US20230195346A1

公开(公告)日：2023-06-22

申请号：US18109774

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Slawomir Putyrski

IPC: G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  G06F9/455 ,  H05K7/14 ,  H04L61/5007 ,  H04L67/63 ,  H04L67/75 ,  H03M7/30 ,  H03M7/40 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L41/044 ,  H04L49/104 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631

CPC classification number: G06F3/0641 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/3079 ,  G06F9/5005 ,  H01R13/4536 ,  H01R13/453 ,  G06F9/5044 ,  G06F9/4843 ,  G06F9/45533 ,  G06F9/5083 ,  H05K7/1491 ,  H04L61/5007 ,  H04L67/63 ,  H04L67/75 ,  G06F3/0608 ,  G06F3/065 ,  G06F3/067 ,  H03M7/6017 ,  H03M7/60 ,  H03M7/40 ,  H03M7/6011 ,  H03M7/6029 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0653 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/3006 ,  G06F11/3409 ,  G06F7/06 ,  G06T9/005 ,  H03M7/3084 ,  H03M7/42 ,  H04L12/2881 ,  H04L12/4633 ,  G06F13/1652 ,  G06F21/6218 ,  G06F21/76 ,  H03K19/1731 ,  H04L9/0822 ,  H04L41/044 ,  H04L49/104 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/505 ,  G06F12/0284 ,  G06F12/0692 ,  G06T1/20 ,  G06T1/60 ,  G06F9/3891 ,  G06F9/5038 ,  G06F9/544 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  G06F3/0604 ,  G06F11/3034 ,  G06F11/3055 ,  H01R13/4538 ,  H01R13/631 ,  H05K7/1452 ,  H05K7/1487 ,  H04L47/78

Abstract: A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.

公开(公告)号：US20220179575A1

公开(公告)日：2022-06-09

申请号：US17681025

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan CUSTODIO ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  G06F9/455 ,  H05K7/14 ,  H03M7/30 ,  H03M7/40 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L61/5007 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L41/044 ,  H04L49/104 ,  H04L67/63 ,  H04L67/75 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US11137922B2

公开(公告)日：2021-10-05

申请号：US15719770

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Rahul Khanna ,  Slawomir Putyrski ,  Sujoy Sen ,  Paul Dormitzer

IPC: G06F9/50 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  H01R13/453 ,  G06F9/48 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14 ,  H04L12/911 ,  G06F11/14 ,  H04L29/06 ,  G06F15/80

Abstract: Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.