公开(公告)号：US20170187283A1

公开(公告)日：2017-06-29

申请号：US14757732

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Vivek K. De ,  Krishnan Ravichandran

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/083 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.

公开(公告)号：US09600283B2

公开(公告)日：2017-03-21

申请号：US14854082

申请日：2015-09-15

Applicant: INTEL CORPORATION

Inventor： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/46

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

公开(公告)号：US20160034338A1

公开(公告)日：2016-02-04

申请号：US14878985

申请日：2015-10-08

Applicant: INTEL CORPORATION

Inventor： Keith A. Bowman ,  James W. Tschanz ,  Nam Sung Kim ,  Janice C. Lee ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Tanay Karnik ,  Vivek K. De

IPC: G06F11/07

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G06F1/10 ,  G06F11/0706 ,  G06F11/0757 ,  G06F11/0793 ,  H03K3/0375

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract translation: 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

公开(公告)号：US10108212B2

公开(公告)日：2018-10-23

申请号：US14861997

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Sunghyun Park ,  Stephen Kim ,  Krishnan Ravichandran ,  Sriram R. Vangal ,  Vivek K. De

IPC: G05F1/575 ,  G05F1/59 ,  H02M1/00 ,  H02M1/08

Abstract: Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.

公开(公告)号：US10069397B2

公开(公告)日：2018-09-04

申请号：US14757802

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Pavan Kumar ,  Krishnan Ravichandran ,  Vivek K. De

IPC: H02M1/08 ,  H02M1/38 ,  H02M3/158

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.

公开(公告)号：US09948179B2

公开(公告)日：2018-04-17

申请号：US15032981

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Pascal A. Meinerzhagen ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

IPC: G05F1/10 ,  G05F3/02 ,  H02M3/07 ,  H02J7/00 ,  G06F3/041 ,  H03K3/037 ,  H03K19/21

CPC classification number: H02M3/073 ,  G06F3/041 ,  H02J7/00 ,  H03K3/0377 ,  H03K19/21

Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

公开(公告)号：US09870012B2

公开(公告)日：2018-01-16

申请号：US13976223

申请日：2012-09-25

Applicant: Intel Corporation

Inventor： Arijit Raychowdhury ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

IPC: G06F1/00 ,  G05F1/577 ,  G05F1/56 ,  G05F1/46 ,  G06F1/06 ,  G06F1/26 ,  H03L7/085

CPC classification number: G05F1/577 ,  G05F1/468 ,  G05F1/56 ,  G06F1/06 ,  G06F1/26 ,  H03L7/085 ,  Y10T307/406

Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.

公开(公告)号：US20170187284A1

公开(公告)日：2017-06-29

申请号：US14757802

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Pavan Kumar ,  Krishnan Ravichandran ,  Vivek K. De

IPC: H02M3/158

CPC classification number: H02M1/083 ,  H02M1/38 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.

公开(公告)号：US20160225438A1

公开(公告)日：2016-08-04

申请号：US14989762

申请日：2016-01-06

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C11/418 ,  G11C8/10

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US20160210192A1

公开(公告)日：2016-07-21

申请号：US15083122

申请日：2016-03-28

Applicant: INTEL CORPORATION

Inventor： Jaydeep P. Kulkarni ,  Keith A. Bowman ,  James W. Tschanz ,  Vivek K. De

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0751 ,  G06F11/1008 ,  G11C7/18 ,  G11C29/42 ,  G11C29/52

Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

Abstract translation: 所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和​​/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高了系统的总体能量效率。