利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.021 秒)

    SILICON WAVEGUIDE ON BULK SILICON SUBSTRATE AND METHODS OF FORMING
    12.
    发明申请
    SILICON WAVEGUIDE ON BULK SILICON SUBSTRATE AND METHODS OF FORMING 有权
    硅基硅衬底上的硅波形和形成方法

    公开(公告)号：US20150340273A1

    公开(公告)日：2015-11-26

    申请号：US14283984

    申请日：2014-05-21

    申请人： International Business Machines Corporation

    发明人： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

    IPC分类号： H01L21/762 ,  G02B6/132 ,  G02B6/136 ,  H01L29/06 ,  G02B6/134

    CPC分类号： H01L21/76224 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12061 ,  H01L21/762 ,  H01L29/06 ,  H01L29/0649

    摘要： Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

    摘要翻译： 各种方法包括：在体硅层中形成光波导，光波导包括覆盖硅衬底区域的一组浅沟槽隔离（STI）区域; 离子注入硅衬底以使硅衬底的一部分非晶化; 通过STI区域形成一组沟槽并进入下面的硅衬底区域; 底切蚀刻在STI区域下方的硅衬底区域通过该组沟槽以形成一组空穴，其中硅衬底的至少部分非晶化部分以小于硅衬底的蚀刻速率的速率蚀刻; 并密封该组腔。

    High linearity SOI wafer for low-distortion circuit applications
    13.
    发明授权
    High linearity SOI wafer for low-distortion circuit applications 有权
    用于低失真电路应用的高线性SOI晶片

    公开(公告)号：US09165819B2

    公开(公告)日：2015-10-20

    申请号：US14546058

    申请日：2014-11-18

    申请人： International Business Machines Corporation

    发明人： Alan B. Botula ,  Jeffrey E. Hanrahan ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Dale W. Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    IPC分类号： H01L21/76 ,  H01L21/04 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

    CPC分类号： H01L21/76251 ,  H01L21/04 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324

    摘要： According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.

    摘要翻译： 根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。 在植入第一种材料之后，第二种材料沉积在基底的第一面上。 绝缘体层的第一面在衬底的第一侧上与第二材料接合。 在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。 集成电路器件进行热退火。 第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

    Bipolar junction transistors with self-aligned terminals
    14.
    发明授权
    Bipolar junction transistors with self-aligned terminals 有权
    具有自对准端子的双极结晶体管

    公开(公告)号：US09059196B2

    公开(公告)日：2015-06-16

    申请号：US14070989

    申请日：2013-11-04

    申请人： International Business Machines Corporation

    发明人： John J. Benoit ,  James R. Elliot ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

    IPC分类号： H01L21/762 ,  H01L29/73 ,  H01L29/66 ,  H01L29/732

    CPC分类号： H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

    摘要： Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

    摘要翻译： 双极结型晶体管的器件结构，设计结构和制造方法。 由包含第一半导体材料的第一层和由第二半导体材料组成的第二层设置在包含双极结型晶体管的第一端子的衬底上。 第二层设置在第一层上，并且在第二层上形成图案化的蚀刻掩模。 沟槽延伸穿过图案硬掩模层，第一层和第二层并进入衬底。 沟槽限定了与第二层的一部分堆叠的第一层的一部分。 使用选择性蚀刻工艺来相对于第一层的截面来缩小第二层的截面以限定第二端子并且加宽衬底中的沟槽的一部分以削弱第一层的部分。

    High resistivity silicon-on-insulator substrate and method of forming
    16.
    发明授权
    High resistivity silicon-on-insulator substrate and method of forming 有权
    高电阻率硅绝缘体基板及其成型方法

    公开(公告)号：US08963293B2

    公开(公告)日：2015-02-24

    申请号：US14151582

    申请日：2014-01-09

    申请人： International Business Machines Corporation

    发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

    IPC分类号： H01L23/58 ,  H01L29/16 ,  H01L21/762

    CPC分类号： H01L29/16 ,  H01L21/76254

    摘要： A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

    摘要翻译： 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

    Low harmonic RF switch in SOI
    18.
    发明授权
    Low harmonic RF switch in SOI 有权
    SOI中的低谐波RF开关

    公开(公告)号：US08722508B2

    公开(公告)日：2014-05-13

    申请号：US13832929

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

    IPC分类号： H01L21/764

    CPC分类号： H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

    摘要： A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

    摘要翻译： 绝缘体上硅（SOI）衬底中的低谐波射频（RF）开关及其制造方法。 一种方法包括通过绝缘体层形成至少一个沟槽。 所述至少一个沟槽与形成在所述绝缘体层上的有源区域中的器件相邻。 该方法还包括在绝缘体层之下的衬底中形成至少一个空腔，并从该至少一个沟槽横向延伸到该器件的下方。

    Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
    19.
    发明授权
    Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure 有权
    配置为减少谐波的绝缘体上硅（SOI）结构和形成结构的方法

    公开(公告)号：US08564067B2

    公开(公告)日：2013-10-22

    申请号：US13772402

    申请日：2013-02-21

    申请人： International Business Machines Corporation

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L21/70

    CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。