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    METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY
    11.
    发明申请
    METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY 有权
    通过选择性外延在BICMOS技术中桥接特征和内在基础的方法

    公开(公告)号：US20150014747A1

    公开(公告)日：2015-01-15

    申请号：US14500021

    申请日：2014-09-29

    Applicant: International Business Machines Corporation

    Inventor： James W. Adkisson ,  Kevin K. Chan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

    IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

    CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

    Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

    Abstract translation: 一种形成异质结双极晶体管的方法。 该方法包括提供包括至少本征基极区域和发射极基座区域的结构。 在本征基区上形成堆叠。 堆叠包括多晶硅层和顶部牺牲氧化物层。 在结构中形成沟槽。 沟槽围绕内在的基极区域和叠层。 在堆叠周围的两个区域形成一个非本征基。 外部基极通过选择性外延生长工艺形成，以在沟槽上形成桥。 桥梁连接两个地区。 在堆栈中提供一个开口。 开口暴露了内在基础区域的一部分。 在开口中形成发射体。

    COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY
    12.
    发明申请
    COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY 有权
    BICMOS技术中收集双极接头晶体管

    公开(公告)号：US20140231877A1

    公开(公告)日：2014-08-21

    申请号：US13769500

    申请日：2013-02-18

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

    IPC: H01L29/66 ,  H01L29/737

    CPC classification number: H01L29/7371 ,  H01L29/0649 ,  H01L29/267 ,  H01L29/66242 ,  H01L29/7327 ,  H01L29/737 ,  H01L29/7378

    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

    Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 在衬底中限定的器件区域中形成发射极。 在发射极上形成一个本征基极。 形成了通过内在基极与发射极分离的集电极。 集电体包括具有大于器件区域的半导体材料的电子带隙的电子带隙的半导体材料。

    BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
    18.
    发明申请
    BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE 有权
    具有降低的基极集电极结电容的双极晶体管

    公开(公告)号：US20150311283A1

    公开(公告)日：2015-10-29

    申请号：US14734713

    申请日：2015-06-09

    Applicant: International Business Machines Corporation

    Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/732

    CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

    Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

    Abstract translation: 双极结型晶体管的器件结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

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