公开(公告)号：US20210110727A1

公开(公告)日：2021-04-15

申请号：US17131256

申请日：2020-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mahmoud Amin ,  Zhenxing Bi ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Christopher J. Penny ,  Krishna R. Tunga ,  Loma Vaishnav

IPC: G09B5/02 ,  G09B19/04 ,  G10L15/26 ,  G09B19/06 ,  G06F16/40 ,  G06F40/40

Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning. Responsive to the individual being a baby, the voice-to-language processor discretizes baby babbling to consonants, letters, and words.

公开(公告)号：US20200013732A1

公开(公告)日：2020-01-09

申请号：US16575549

申请日：2019-09-19

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Krishna R. Tunga ,  Hilton T. Toy ,  Thomas Weiss ,  Shidong Li ,  Sushumna Iruvanti

IPC: H01L23/00 ,  H05K3/30 ,  H01L23/498 ,  H01L21/48 ,  H01L21/027

Abstract: A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.

公开(公告)号：US20180108626A1

公开(公告)日：2018-04-19

申请号：US15642742

申请日：2017-07-06

Applicant: International Business Machines Corporation

Inventor： Ekta Misra ,  Krishna R. Tunga

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20180061800A1

公开(公告)日：2018-03-01

申请号：US15794192

申请日：2017-10-26

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/17133 ,  H01L2924/3512

Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

公开(公告)号：US11282773B2

公开(公告)日：2022-03-22

申请号：US16845404

申请日：2020-04-10

Applicant: International Business Machines Corporation

Inventor： Krishna R. Tunga ,  Thomas Weiss ,  Charles Leon Arvin ,  Bhupender Singh ,  Brian W. Quinlan

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/50 ,  H01L23/00 ,  H01L21/60

Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

公开(公告)号：US20210242139A1

公开(公告)日：2021-08-05

申请号：US16779529

申请日：2020-01-31

Applicant: International Business Machines Corporation

Inventor： Tuhin Sinha ,  Krishna R. Tunga ,  Brian W. Quinlan ,  Charles Leon Arvin ,  Steven Paul Ostrander ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/14 ,  H01L21/48 ,  H01L23/66 ,  H01L23/538

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

公开(公告)号：US10950573B2

公开(公告)日：2021-03-16

申请号：US16358658

申请日：2019-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Clement J. Fortin ,  Christopher D. Muzzy ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/532

Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.

公开(公告)号：US10325830B1

公开(公告)日：2019-06-18

申请号：US15826856

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Steven P. Ostrander ,  Krishna R. Tunga

IPC: F28F21/08 ,  H01L21/48 ,  H01L23/367 ,  H01L23/373

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

公开(公告)号：US20190148260A1

公开(公告)日：2019-05-16

申请号：US15812290

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Hilton T. Toy ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/367 ,  H01L23/053 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L23/3675 ,  H01L23/053 ,  H01L23/10 ,  H01L23/433 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/9221 ,  H01L2924/1432 ,  H01L2924/3511

Abstract: An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.

公开(公告)号：US10108753B2

公开(公告)日：2018-10-23

申请号：US15176101

申请日：2016-06-07

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

IPC: G06F17/50

Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.