Patent search ap:("International Business Machines Corporation") AND inv:"Brian R. Sundlof" Page 2

11.

发明授权
Determining crackstop strength of integrated circuit assembly at the wafer level 有权

公开(公告)号：US09947598B1

公开(公告)日：2018-04-17

申请号：US15634237

申请日：2017-06-27

Applicant: International Business Machines Corporation

Inventor： Krishna R. Tunga , Karen P. McLaughlin , Charles L. Arvin , Brian R. Sundlof , Steven P. Ostrander , Christopher D. Muzzy , Thomas A. Wassick

IPC: H01L21/66 , H01L23/58 , H01L21/78

CPC classification number: H01L22/12 , H01L21/78 , H01L23/585

Abstract: A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).

12.

发明申请
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT 有权

公开(公告)号：US20180012838A1

公开(公告)日：2018-01-11

申请号：US15207077

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof

IPC: H01L23/522 , H01L23/00

CPC classification number: H01L23/5223 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/50 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/81 , H01L2224/16225 , H01L2224/73253 , H01L2224/81815 , H01L2924/15311 , H01L2924/16152 , H01L2924/19103

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc. includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

13.

发明授权
Additives for grain fragmentation in Pb-free Sn-based solder 有权
Title translation: 在无铅锡基焊料中颗粒破碎的添加剂

公开(公告)号：US08910853B2

公开(公告)日：2014-12-16

申请号：US13932070

申请日：2013-07-01

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S.N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman

IPC: B23K31/02 , H01L21/44 , B23K35/36 , C22C13/00 , B23K35/02 , B23K35/26 , H01L23/498 , H01B13/00 , H01B1/02 , H05K3/34 , B82Y30/00

CPC classification number: H01B1/02 , B23K35/0244 , B23K35/262 , B23K35/36 , B23K35/3602 , B82Y30/00 , C22C13/00 , H01B13/00 , H01L23/49866 , H01L2924/0002 , H05K3/3436 , H05K3/3463 , H05K2201/0209 , H05K2201/0257 , Y10T29/49117 , H01L2924/00

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

14.

发明授权
Multilayer pillar for reduced stress interconnect and method of making same 有权

公开(公告)号：US11094657B2

公开(公告)日：2021-08-17

申请号：US16502591

申请日：2019-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof

IPC: H01L23/00

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

15.

发明申请
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT 审中-公开

公开(公告)号：US20190172784A1

公开(公告)日：2019-06-06

申请号：US16269730

申请日：2019-02-07

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof

IPC: H01L23/522 , H01L23/498 , H01L23/50 , H01L23/00

Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

16.

发明申请
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT 审中-公开

公开(公告)号：US20180068945A1

公开(公告)日：2018-03-08

申请号：US15796782

申请日：2017-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof

IPC: H01L23/522 , H01L23/00

CPC classification number: H01L23/5223 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/50 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/18 , H01L2224/13101 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2924/15311 , H01L2924/16152 , H01L2924/19103 , H01L2924/19107 , H01L2924/014 , H01L2924/00014 , H01L2924/00

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

17.

发明授权
Multi terminal capacitor within input output path of semiconductor package interconnect 有权

公开(公告)号：US09899313B2

公开(公告)日：2018-02-20

申请号：US15207077

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof

IPC: H01L23/52 , H01L23/538 , H01L23/522 , H01L23/00

CPC classification number: H01L23/5223 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/50 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/81 , H01L2224/16225 , H01L2224/73253 , H01L2224/81815 , H01L2924/15311 , H01L2924/16152 , H01L2924/19103

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.