公开(公告)号：US20060219573A1

公开(公告)日：2006-10-05

申请号：US11445594

申请日：2006-06-01

申请人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

发明人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

IPC分类号： B23H3/00

CPC分类号： B24B37/20 ,  B24B37/046 ,  B24B37/24 ,  B24B37/26 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/2885 ,  H01L21/76877

摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.

摘要翻译： 本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。 这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。 在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上， 在工件和阳极之间施加电位差。 在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。 在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

公开(公告)号：US20060165911A1

公开(公告)日：2006-07-27

申请号：US11278664

申请日：2006-04-04

申请人： Bulent Basol

发明人： Bulent Basol

IPC分类号： B05D1/04

CPC分类号： C23C8/02 ,  C23C10/02 ,  C23C10/06 ,  C23C12/00 ,  H01L31/0322 ,  H01L31/18 ,  Y02E10/541

摘要： A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.

摘要翻译： 形成化合物膜的方法包括配制具有受控整体组成的纳米粉末材料并且包括一种固溶体的颗粒将纳米粉末材料沉积在基底上以在基底上形成层，并且该层在 至少一种合适的气氛形成复合膜。 复合膜可用于制造辐射检测器或太阳能电池。

公开(公告)号：US20060070885A1

公开(公告)日：2006-04-06

申请号：US11295014

申请日：2005-12-06

申请人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

发明人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D5/02 ,  C25D5/48

CPC分类号： C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

公开(公告)号：US20060042934A1

公开(公告)日：2006-03-02

申请号：US11259694

申请日：2005-10-25

申请人： Homayoun Talieh ,  Bulent Basol

发明人： Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D17/00

CPC分类号： H01L21/6715 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/67075

摘要： The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other. In an alternative embodiment, electrical contacts may be formed using an inflatable tube that has either been coated with a conductive material or contains a conductive object. The inflatable tube further provides uniform contact and pressure along the periphery of the workpiece, which may not necessarily be perfectly flat, because the tube can conform according to the shape of the periphery of the workpiece. Further, the present invention can be used to dissolve/etch a metal layer from the periphery of the workpiece.

公开(公告)号：US06974769B2

公开(公告)日：2005-12-13

申请号：US10663318

申请日：2003-09-16

申请人： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

发明人： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/7684

摘要： Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.

摘要翻译： 通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。 在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。 然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。 然后去除过量的导电材料以露出场区并留下导电结构。 施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。 这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。 优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。

公开(公告)号：US20050150777A1

公开(公告)日：2005-07-14

申请号：US11011529

申请日：2004-11-19

申请人： Bulent Basol

发明人： Bulent Basol

IPC分类号： B24B37/04 ,  C25F3/02 ,  H01L21/321 ,  B23H5/00

CPC分类号： B24B37/042 ,  B24B37/015 ,  B24B37/046 ,  C25F3/02 ,  H01L21/32115

摘要： A system and method for removal and planarization of conductive material on a semiconductor substrate using an electrode contacting a solution. Physical contact is established between the conductive material and the solution. A buffer layer on the conductive material is formed by varying the temperature of the conductive material. A potential difference is applied between the conductive material and the electrode and the buffer layer is removed from raised regions of the conductive material by electropolishing the raised regions with the solution while the recessed regions of the conductive material are covered by the buffer layer.

摘要翻译： 一种使用接触溶液的电极在半导体衬底上去除和平坦化导电材料的系统和方法。 在导电材料和溶液之间建立物理接触。 通过改变导电材料的温度来形成导电材料上的缓冲层。 在导电材料和电极之间施加电位差，并且通过用溶液电解抛光凸起区域，而导电材料的凹陷区域被缓冲层覆盖，从导电材料的凸起区域去除缓冲层。

公开(公告)号：US06905588B2

公开(公告)日：2005-06-14

申请号：US09905335

申请日：2001-07-13

申请人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol

发明人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D3/02 ,  C23C28/00 ,  C25D5/10 ,  C25D7/12 ,  H01L21/288 ,  H01L21/304 ,  H01L21/60 ,  H01L21/768 ,  C25D5/00 ,  B23H3/00

CPC分类号： C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

摘要翻译： 本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。 这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。 另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。 本发明还公开了用于形成多级互连的方法和相应的结构。

公开(公告)号：US20050112868A1

公开(公告)日：2005-05-26

申请号：US10719909

申请日：2003-11-21

申请人： Bulent Basol

发明人： Bulent Basol

IPC分类号： C25F3/02 ,  C25F7/00 ,  H01L21/321 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/32115 ,  C25F3/02 ,  C25F7/00 ,  H01L21/7684

摘要： An apparatus for electropolishing a conductive material layer is disclosed. The apparatus comprises a porous conductive member configured to contact the conductive layer and having a first connector for receiving electrical power, an electrode insulatively coupled to the porous conductive member having a second connector configured to receive electrical power, a holder insulatively coupled to the porous conductive member and the electrode configured to establish relative motion between the porous conductive member and the conductive layer, and a power supply coupled to the first connector and the second connector configured to supply the electrical power between the electrode and the porous conductive member for electropolishing the conductive layer.

摘要翻译： 公开了一种用于电解抛光导电材料层的装置。 所述设备包括多孔导电构件，其被配置为接触所述导电层并且具有用于接收电力的第一连接器，绝缘地连接到所述多孔导电构件的电极，所述多孔导电构件具有被配置为接收电力的第二连接器，与所述多孔导电体绝缘耦合的保持器 所述电极构造成在所述多孔导电构件和所述导电层之间建立相对运动;以及电源，其耦合到所述第一连接器和所述第二连接器，所述电源被配置为在所述电极和所述多孔导电构件之间提供电功率，以电抛光所述导电 层。

公开(公告)号：US20050095846A1

公开(公告)日：2005-05-05

申请号：US10979341

申请日：2004-11-01

申请人： Bulent Basol

发明人： Bulent Basol

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

摘要： A system and method for depositing a defect-free conductor on semiconductor substrates having features and seed layers with defective regions. A repair layer is deposited over the seed layer and the defective regions in a deposition module within a housing. The repair layer can be deposited by atomic layer deposition or chemical vapor deposition. A conductive material is then electroplated over the seed layer to fill the features and form a defect-free conductive layer over the top surface of the substrate. The electroplating is performed in another deposition module within the housing.

摘要翻译： 一种用于在具有缺陷区域的特征和种子层的半导体衬底上沉积无缺陷导体的系统和方法。 修复层沉积在种子层上并且在壳体内的沉积模块中的缺陷区域上沉积。 可以通过原子层沉积或化学气相沉积来沉积修复层。 然后将导电材料电镀在种子层上以填充特征并在衬底的顶表面上形成无缺陷的导电层。 电镀在外壳内的另一沉积模块中进行。

公开(公告)号：US06855037B2

公开(公告)日：2005-02-15

申请号：US09910686

申请日：2001-07-20

申请人： Jalal Ashjaee ,  Homayoun Talieh ,  Bulent Basol ,  Konstantin Volodarsky

发明人： Jalal Ashjaee ,  Homayoun Talieh ,  Bulent Basol ,  Konstantin Volodarsky

IPC分类号： B24B37/30 ,  C25D7/12 ,  C25D17/06 ,  H01L21/00 ,  H01L21/683 ,  B24B1/00

CPC分类号： B24B37/30 ,  C25D17/001 ,  C25D17/06 ,  H01L21/6704 ,  H01L21/6715 ,  H01L21/6838

摘要： The present invention provides a wafer carrier that includes an opening, which in one embodiment is a plurality of holes, disposed along the periphery of the wafer carrier. A gas emitted through the holes onto a peripheral back edge of the wafer assists in preventing the processing liquids and contaminants resulting therefrom from reaching the inner region of the base and the backside inner region of the wafer. In another embodiment, a plurality of concentric sealing members are used to prove a better seal, and the outer seal is preferably independently movable to allow cleaning of a peripheral backside of the wafer to occur while the wafer is still attached to the wafer carrier.

摘要翻译： 本发明提供了一种晶片载体，其包括沿着晶片载体的周边设置的开口，其在一个实施例中是多个孔。 通过孔发射到晶片的外围后缘上的气体有助于防止由此产生的处理液体和污染物到达晶片的底部和内侧区域的内部区域。 在另一个实施例中，使用多个同心密封构件来证明更好的密封，并且外部密封件优选地是独立地可移动的，以允许当晶片仍然附接到晶片载体时清洁晶片的周边背面而发生。