公开(公告)号：US5229323A

公开(公告)日：1993-07-20

申请号：US846985

申请日：1992-03-09

申请人： Kizashi Shimada ,  Tatsuo Akiyama ,  Yutaka Koshino

发明人： Kizashi Shimada ,  Tatsuo Akiyama ,  Yutaka Koshino

IPC分类号： H01L21/263 ,  H01L21/285 ,  H01L21/338

CPC分类号： H01L29/66863 ,  H01L21/2633 ,  H01L21/28581 ,  Y10S148/139 ,  Y10S148/14

摘要： A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.

摘要翻译： 制造具有肖特基电极的半导体器件的方法包括以下步骤：在溅射装置的溅射处理室中对GaAs衬底的表面进行溅射蚀刻工艺; 并通过溅射将肖特基电极材料沉积在衬底的表面上以在处理室中形成肖特基电极，而不将衬底暴露于大气中。

公开(公告)号：US4984052A

公开(公告)日：1991-01-08

申请号：US418587

申请日：1989-10-10

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S257/914

摘要： A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.

摘要翻译： 键合衬底包括其中形成有多个半导体元件的第一半导体衬底，第二半导体衬底，其粘附到第一半导体衬底，以便通过插入其间的绝缘层来支撑它;第一半绝缘多晶硅层， 在第一半导体衬底和绝缘层之间，以及插入在绝缘层和第二半导体衬底之间的第二半绝缘多晶硅层。 半绝缘多晶硅层用于降低施加到绝缘层的电压并防止绝缘层被蚀刻。

公开(公告)号：US4560642A

公开(公告)日：1985-12-24

申请号：US632239

申请日：1984-07-19

申请人： Toshio Yonezawa ,  Takashi Ajima ,  Shunichi Hiraki ,  Yutaka Koshino ,  Yoshitami Oka

发明人： Toshio Yonezawa ,  Takashi Ajima ,  Shunichi Hiraki ,  Yutaka Koshino ,  Yoshitami Oka

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/314 ,  B05D1/32

CPC分类号： H01L21/31144 ,  H01L21/033 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/314 ,  Y10S438/945 ,  Y10S438/95 ,  Y10S438/951

摘要： A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：选择性地施加具有规定穿孔图案的碳化硅膜作为掩模膜，以蚀刻二氧化硅膜或将杂质扩散到衬底中。

公开(公告)号：US5031021A

公开(公告)日：1991-07-09

申请号：US905958

申请日：1986-09-11

申请人： Yoshiro Baba ,  Kazuo Tsuru ,  Tatsuo Akiyama ,  Yutaka Koshino

发明人： Yoshiro Baba ,  Kazuo Tsuru ,  Tatsuo Akiyama ,  Yutaka Koshino

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/04 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732

CPC分类号： H01L29/405 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/408

摘要： There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 .ANG..

摘要翻译： 公开了一种功率晶体管，其包括具有在该半导体衬底的主表面上露出的PN结的半导体衬底和形成在该主表面上的半绝缘性多晶硅膜，该多晶硅膜覆盖该PN结，该多晶硅膜含有至少一个 的碳，氧和氮，以及多晶硅膜的厚度约为3000纳米。

公开(公告)号：US4729966A

公开(公告)日：1988-03-08

申请号：US843833

申请日：1986-03-26

申请人： Yutaka Koshino ,  Tatsuo Akiyama ,  Shunichi Hiraki

发明人： Yutaka Koshino ,  Tatsuo Akiyama ,  Shunichi Hiraki

IPC分类号： H01L29/812 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L29/417 ,  H01L21/225 ,  H01L29/72 ,  H01L29/80

CPC分类号： H01L29/66878 ,  H01L21/2815 ,  H01L21/28587

摘要： A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film. The drain region consists of a high-concentration impurity layer, which is formed such that it is surrounded by the channel positioned inside the substrate on the inside of the second insulative film.

摘要翻译： 第一绝缘膜在肖特基结半导体衬底的表面上以环形形成预定的高度和厚度。 栅极电极金属膜沿着第一绝缘膜的内表面在基板的表面上以环形形成预定的高度和厚度。 第二绝缘膜沿着金属膜的内表面在基板的表面上以环形形成预定的高度和厚度。 由低浓度杂质层构成的通道在金属膜正下方的基板内部以及第一绝缘膜和第二绝缘膜之间形成为环状。 源极区域由高浓度杂质层构成，其形成为使得其围绕位于第一绝缘膜外侧的衬底内的沟道。 漏极区域由高浓度杂质层构成，其形成为被位于第二绝缘膜内侧的位于基板内部的沟道包围。

公开(公告)号：US4532004A

公开(公告)日：1985-07-30

申请号：US636221

申请日：1984-07-31

申请人： Tatsuo Akiyama ,  Yutaka Koshino ,  Shunichi Hiraki

发明人： Tatsuo Akiyama ,  Yutaka Koshino ,  Shunichi Hiraki

IPC分类号： H01L21/033 ,  H01L21/285 ,  H01L21/338 ,  H01L29/417 ,  H01L29/80 ,  H01L29/812 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L29/66871 ,  H01L21/033 ,  H01L21/28587 ,  H01L29/80 ,  H01L29/812

摘要： A method of manufacturing a GaAs FET is disclosed. In this manufacturing method, a protection film is formed on a GaAs substrate and a dummy gate electrode is formed thereon. A channel length setting film is isotropically formed on the dummy gate electrode to have a constant thickness. Then, an impurity is ion-implanted in the channel length setting film. Thereafter, the channel length setting film is removed. An etching preventive film is anisotropically formed along a substantially vertical direction with respect to the GaAs substrate. The dummy gate electrode is etched using the etching preventive film as a mask so as to form a first opening in the etching preventive film. Then, a second opening is formed in the region of the protection film corresponding to the region in which the dummy gate electrode was present. A gate electrode is formed to be in contact with the GaAs substrate through the first and second openings.

摘要翻译： 公开了一种制造GaAs FET的方法。 在该制造方法中，在GaAs衬底上形成保护膜，在其上形成虚拟栅电极。 通道长度设定膜在虚拟栅电极上各向同性地形成，以具有恒定的厚度。 然后，在沟道长度设定膜中离子注入杂质。 此后，去除通道长度设定膜。 蚀刻防止膜相对于GaAs衬底沿大致垂直方向各向异性地形成。 使用防蚀膜作为掩模蚀刻伪栅电极，以在防蚀膜中形成第一开口。 然后，在保护膜的与存在虚拟栅电极的区域相对应的区域中形成第二开口。 栅电极通过第一和第二开口形成为与GaAs衬底接触。

公开(公告)号：US4351894A

公开(公告)日：1982-09-28

申请号：US262938

申请日：1981-05-12

申请人： Toshio Yonezawa ,  Takashi Ajima ,  Shunichi Hiraki ,  Yutaka Koshino ,  Yoshitami Oka

发明人： Toshio Yonezawa ,  Takashi Ajima ,  Shunichi Hiraki ,  Yutaka Koshino ,  Yoshitami Oka

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316

CPC分类号： H01L21/31144 ,  H01L21/033 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/314 ,  Y10S438/945 ,  Y10S438/95 ,  Y10S438/951

摘要： A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：选择性地施加具有规定穿孔图案的碳化硅膜作为掩模膜，以蚀刻二氧化硅膜或将杂质扩散到衬底中。

公开(公告)号：US5126817A

公开(公告)日：1992-06-30

申请号：US596286

申请日：1990-10-12

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Kenji Yamawaki

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Kenji Yamawaki

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286

摘要： A dielectrically isolated structure for use in an SOI-type semiconductor device according to the present invention comprises a substrate having an element-forming region formed therein on a first insulating film, the region being made of a first material, at least one trench formed in the element-forming region and extending to the first insulating film, second insulating films formed on side walls of the trench, and a film made of a second material, and embedded in only an upper portion of the trench such that a bottom portion of the trench is hollow.

摘要翻译： 根据本发明的用于SOI型半导体器件的介电隔离结构包括在第一绝缘膜上形成有元件形成区域的衬底，该区域由第一材料制成，至少一个沟槽形成在 元件形成区域并延伸到第一绝缘膜，形成在沟槽的侧壁上的第二绝缘膜和由第二材料制成的膜，并且仅嵌入在沟槽的上部中，使得底部部分 沟是空心的

公开(公告)号：US5084408A

公开(公告)日：1992-01-28

申请号：US596294

申请日：1990-10-15

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76283 ,  H01L21/76286 ,  Y10S438/978

摘要： For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.

公开(公告)号：US5029324A

公开(公告)日：1991-07-02

申请号：US512013

申请日：1990-04-16

申请人： Akihiko Osawa ,  Yutaka Koshino ,  Yoshiro Baba

发明人： Akihiko Osawa ,  Yutaka Koshino ,  Yoshiro Baba

IPC分类号： H01L21/60 ,  H01L21/314 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/408 ,  H01L23/29 ,  H01L23/53271 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05686 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/3025

摘要： A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.