公开(公告)号：US07598617B2

公开(公告)日：2009-10-06

申请号：US11647703

申请日：2006-12-29

申请人： Seung Hyun Lee ,  Min Suk Suh

发明人： Seung Hyun Lee ,  Min Suk Suh

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack package includes a printed circuit board; at least two semiconductor chips stacked on the printed circuit board, each having first re-distribution lines formed on the upper surface thereof and connected to bonding pads, through silicon vias which are formed therethrough and connected to the first re-distribution lines, and second re-distribution lines formed on the lower surface thereof and connected to the through silicon vias; first and second solder balls interposed between the first and second re-distribution lines which face each other and between the first re-distribution lines of the lowermost semiconductor chip and electrode terminals of the printed circuit board; a molding material for molding the upper surface of the printed circuit board including the stacked semiconductor chips; and third solder balls attached to ball lands formed on the lower surface of the printed circuit board.

摘要翻译： 堆叠包装包括印刷电路板; 堆叠在印刷电路板上的至少两个半导体芯片，每个半导体芯片具有形成在其上表面上的第一重新分配线，并且通过形成在其中并连接到第一再分配线的硅通孔连接到接合焊盘，第二 再分配线形成在其下表面并连接到通孔硅通孔; 介于第一和第二再分配线之间的第一和第二焊球，它们彼此相对并且在最下半导体芯片的第一重新分配线与印刷电路板的电极端之间; 用于模制包括堆叠的半导体芯片的印刷电路板的上表面的模制材料; 以及附接到形成在印刷电路板的下表面上的球场的第三焊球。

公开(公告)号：US20100187676A1

公开(公告)日：2010-07-29

申请号：US12489626

申请日：2009-06-23

申请人： Min Suk Suh ,  Seung Hyun Lee

发明人： Min Suk Suh ,  Seung Hyun Lee

IPC分类号： H01L23/498

CPC分类号： H01L23/481 ,  H01L24/17 ,  H01L24/24 ,  H01L24/29 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16146 ,  H01L2224/24145 ,  H01L2224/29101 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00

摘要： A cube semiconductor package includes one or more stacked together and interconnected semiconductor chip modules. The cube semiconductor package includes a semiconductor chip module and connection members. The semiconductor chip module includes a semiconductor chip which has a first and second surface, side surfaces, bonding pads, through-electrodes and redistribution lines. The second surface faces away from the first surface. The side surfaces connect to the first and second surfaces. The bonding pads are placed on the first surface. The through-electrodes pass through the first and second surfaces. The redistribution lines are placed at least on one of the first and second surfaces and are electrically connected to the through-electrodes and the bonding pads, and have ends flush with the side surfaces. The connection members are placed on the side surfaces and electrically connected with the ends of the redistribution lines.

摘要翻译： 立体半导体封装包括一个或多个堆叠在一起并且互连的半导体芯片模块。 立方体半导体封装包括半导体芯片模块和连接构件。 半导体芯片模块包括具有第一和第二表面，侧表面，接合焊盘，通孔和再分配线的半导体芯片。 第二表面背离第一表面。 侧表面连接到第一和第二表面。 接合垫被放置在第一表面上。 贯通电极通过第一和第二表面。 再分布线至少放置在第一表面和第二表面中的一个上，并且电连接到通孔和接合焊盘，并且具有与侧表面齐平的端部。 连接构件放置在侧面上并与再分配线的端部电连接。

公开(公告)号：US20070222050A1

公开(公告)日：2007-09-27

申请号：US11647703

申请日：2006-12-29

申请人： Seung Hyun Lee ,  Min Suk Suh

发明人： Seung Hyun Lee ,  Min Suk Suh

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack package includes a printed circuit board; at least two semiconductor chips stacked on the printed circuit board, each having first re-distribution lines formed on the upper surface thereof and connected to bonding pads, through silicon vias which are formed therethrough and connected to the first re-distribution lines, and second re-distribution lines formed on the lower surface thereof and connected to the through silicon vias; first and second solder balls interposed between the first and second re-distribution lines which face each other and between the first re-distribution lines of the lowermost semiconductor chip and electrode terminals of the printed circuit board; a molding material for molding the upper surface of the printed circuit board including the stacked semiconductor chips; and third solder balls attached to ball lands formed on the lower surface of the printed circuit board.

摘要翻译： 堆叠包装包括印刷电路板; 堆叠在印刷电路板上的至少两个半导体芯片，每个半导体芯片具有形成在其上表面上的第一重新分配线，并且通过形成在其中并连接到第一再分配线的硅通孔连接到接合焊盘，第二 再分配线形成在其下表面并连接到通孔硅通孔; 介于第一和第二再分配线之间的第一和第二焊球，它们彼此相对并且在最下半导体芯片的第一重新分配线与印刷电路板的电极端之间; 用于模制包括堆叠的半导体芯片的印刷电路板的上表面的模制材料; 以及附接到形成在印刷电路板的下表面上的球场的第三焊球。

公开(公告)号：US08232654B2

公开(公告)日：2012-07-31

申请号：US13089666

申请日：2011-04-19

申请人： Min Suk Suh

发明人： Min Suk Suh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/83138 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

摘要： A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.

摘要翻译： 公开了一种半导体封装，其包括用于堆叠半导体封装的通孔和具有该半导体封装的半导体封装。 半导体封装通孔包括第一电极，其中形成有用于穿过半导体芯片的凹部。 第二电极设置在第一电极的凹部内。 半导体封装通孔的第一电极包括具有第一硬度的第一金属，第二电极包括具有低于第一硬度的第二硬度的第二金属。 贯通电极通过半导体芯片体，并且可以形成具有第一硬度和/或第一熔点的第一金属和具有第二硬度和/或第二熔点的第二金属，该第二金属低于第一硬度 硬度和/或第一熔点。 该贯通电极允许容易堆叠多个半导体封装。

公开(公告)号：US20080001304A1

公开(公告)日：2008-01-03

申请号：US11647621

申请日：2006-12-29

申请人： Sung Min Kim ,  Min Suk Suh ,  Kwon Whan Han

发明人： Sung Min Kim ,  Min Suk Suh ,  Kwon Whan Han

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stack package includes an edge-pad-type first semiconductor chip having bonding pads arranged near the edges thereof. A pattern die is placed on the first semiconductor chip. The pattern die is smaller in size than the first semiconductor chip and has line-type-redistribution parts formed thereon. An edge-pad-type second semiconductor chip smaller in size than the pattern die is placed on the pattern die. Bonding wires electrically connect the bonding pads of the first semiconductor chip and the redistribution parts of the pattern die and also electrically connect the redistribution parts of the pattern die and bonding pads of the second semiconductor chip.

摘要翻译： 堆叠封装包括边缘焊盘型第一半导体芯片，其具有布置在其边缘附近的焊盘。 图案裸片放置在第一半导体芯片上。 图案芯片的尺寸小于第一半导体芯片，并且在其上形成线型再分配部件。 尺寸小于图案裸片的边缘焊盘型第二半导体芯片被放置在图案芯片上。 接合线电连接第一半导体芯片的接合焊盘和图案芯片的再分配部分，并且还将图形芯片的再分配部分和第二半导体芯片的焊盘电连接。

公开(公告)号：US08203217B2

公开(公告)日：2012-06-19

申请号：US13024631

申请日：2011-02-10

申请人： Min Suk Suh

发明人： Min Suk Suh

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/19

摘要： A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region.

摘要翻译： 具有层叠晶片级结构的半导体封装包括基底; 半导体芯片; 再分配模式; 和第二绝缘层图案。 基底部具有芯片区域和设置在芯片区域周边的周边区域。 半导体芯片设置在芯片区域上并具有接合焊盘。 第一绝缘层图案覆盖芯片区域和周边区域并且暴露接合焊盘。 再分配图案设置在第一绝缘层图案上并且从接合垫延伸到周边区域。 第二绝缘层图案设置在第一绝缘层图案之上并且打开布置在周边区域中的再分布图案的一部分。

公开(公告)号：US08202762B2

公开(公告)日：2012-06-19

申请号：US13218916

申请日：2011-08-26

申请人： Sung Min Kim ,  Min Suk Suh

发明人： Sung Min Kim ,  Min Suk Suh

IPC分类号： H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2224/05099

摘要： A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

摘要翻译： 堆叠封装包括上半导体芯片，其具有形成在上半导体芯片的上表面上的多个第一焊盘和在相应的第一焊盘下方的上半导体芯片中限定的通孔; 以及下半导体芯片，其安装在上半导体芯片的下表面，并且具有多个第二焊盘，其形成在下半导体芯片的上表面上，并且形成在各个第二焊盘上并被插入 各个通孔将进入相应的第一接合焊盘。

公开(公告)号：US07923294B2

公开(公告)日：2011-04-12

申请号：US12765221

申请日：2010-04-22

申请人： Min Suk Suh

发明人： Min Suk Suh

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.

摘要翻译： 半导体封装及其制造方法。 半导体封装包括具有接合焊盘的半导体芯片; 第一绝缘层图案; 再分配线模式; 第二绝缘层图案; 和导电球。 第一绝缘层图案具有暴露接合焊盘的第一开口。 再分配线图案位于第一绝缘层图案上，并且与接合焊盘电连接。 第二绝缘层图案覆盖再分布线图案并且具有第二开口，该第二开口具有暴露重分布线图案的部分并且具有沿着半导体芯片从第一开放区域延伸的第二开放区域的第一开口区域。 导电球与通过第二绝缘层图案的第一开放区域暴露的再分布线图案的部分电连接。

公开(公告)号：US07732931B2

公开(公告)日：2010-06-08

申请号：US12044178

申请日：2008-03-07

申请人： Min Suk Suh

发明人： Min Suk Suh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.

摘要翻译： 半导体封装及其制造方法。 半导体封装包括具有接合焊盘的半导体芯片; 第一绝缘层图案; 再分配线模式; 第二绝缘层图案; 和导电球。 第一绝缘层图案具有暴露接合焊盘的第一开口。 再分配线图案位于第一绝缘层图案上，并且与接合焊盘电连接。 第二绝缘层图案覆盖再分布线图案并且具有第二开口，该第二开口具有暴露重分布线图案的部分并且具有沿着半导体芯片从第一开放区域延伸的第二开放区域的第一开口区域。 导电球与通过第二绝缘层图案的第一开放区域暴露的再分布线图案的部分电连接。

公开(公告)号：US07525186B2

公开(公告)日：2009-04-28

申请号：US11647704

申请日：2006-12-29

申请人： Sung Min Kim ,  Min Suk Suh

发明人： Sung Min Kim ,  Min Suk Suh

IPC分类号： H01L25/07 ,  H01L25/18 ,  H01L23/02 ,  H01L23/055 ,  H01L23/12 ,  H01L29/00

CPC分类号： H01L21/76898 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

摘要： A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

摘要翻译： 堆叠封装包括具有电路图案的衬底; 堆叠在基板上的至少两个半导体芯片，具有多个通孔互连插头和围绕相应通孔互连插头的多个保护环，并且通过通孔互连插头的介质彼此连接 ; 用于模制包括堆叠的半导体芯片的基板的上表面的模制材料; 以及安装到基板的下表面的焊球。