公开(公告)号：US07834463B2

公开(公告)日：2010-11-16

申请号：US11647621

申请日：2006-12-29

申请人： Sung Min Kim ,  Min Suk Suh ,  Kwon Whan Han

发明人： Sung Min Kim ,  Min Suk Suh ,  Kwon Whan Han

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stack package includes an edge-pad-type first semiconductor chip having bonding pads arranged near the edges thereof. A pattern die is placed on the first semiconductor chip. The pattern die is smaller in size than the first semiconductor chip and has line-type-redistribution parts formed thereon. An edge-pad-type second semiconductor chip smaller in size than the pattern die is placed on the pattern die. Bonding wires electrically connect the bonding pads of the first semiconductor chip and the redistribution parts of the pattern die and also electrically connect the redistribution parts of the pattern die and bonding pads of the second semiconductor chip.

摘要翻译： 堆叠封装包括边缘焊盘型第一半导体芯片，其具有布置在其边缘附近的焊盘。 图案裸片放置在第一半导体芯片上。 图案芯片的尺寸小于第一半导体芯片，并且在其上形成线型再分配部件。 尺寸小于图案裸片的边缘焊盘型第二半导体芯片被放置在图案芯片上。 接合线电连接第一半导体芯片的接合焊盘和图案芯片的再分配部分，并且还将图案芯片的再分配部分和第二半导体芯片的焊盘电连接。

公开(公告)号：US07795139B2

公开(公告)日：2010-09-14

申请号：US11777388

申请日：2007-07-13

申请人： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

发明人： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

摘要翻译： 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US20080001304A1

公开(公告)日：2008-01-03

申请号：US11647621

申请日：2006-12-29

申请人： Sung Min Kim ,  Min Suk Suh ,  Kwon Whan Han

发明人： Sung Min Kim ,  Min Suk Suh ,  Kwon Whan Han

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stack package includes an edge-pad-type first semiconductor chip having bonding pads arranged near the edges thereof. A pattern die is placed on the first semiconductor chip. The pattern die is smaller in size than the first semiconductor chip and has line-type-redistribution parts formed thereon. An edge-pad-type second semiconductor chip smaller in size than the pattern die is placed on the pattern die. Bonding wires electrically connect the bonding pads of the first semiconductor chip and the redistribution parts of the pattern die and also electrically connect the redistribution parts of the pattern die and bonding pads of the second semiconductor chip.

摘要翻译： 堆叠封装包括边缘焊盘型第一半导体芯片，其具有布置在其边缘附近的焊盘。 图案裸片放置在第一半导体芯片上。 图案芯片的尺寸小于第一半导体芯片，并且在其上形成线型再分配部件。 尺寸小于图案裸片的边缘焊盘型第二半导体芯片被放置在图案芯片上。 接合线电连接第一半导体芯片的接合焊盘和图案芯片的再分配部分，并且还将图形芯片的再分配部分和第二半导体芯片的焊盘电连接。

公开(公告)号：US07795073B2

公开(公告)日：2010-09-14

申请号：US12345858

申请日：2008-12-30

申请人： Kwon Whan Han ,  Chang Jun Park ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee

发明人： Kwon Whan Han ,  Chang Jun Park ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/16 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/17 ,  H01L24/90 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/90 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

摘要： Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.

摘要翻译： 制造晶片级堆叠封装包括对包括多个第一半导体芯片的晶片的下表面进行背面磨削的步骤。 支撑构件附接到后磨碎晶片的下表面。 一个或多个第二半导体芯片堆叠在背面研磨的晶片的相应的第一半导体芯片上。 形成第一贯通电极以电连接堆叠的第一半导体芯片和第二半导体芯片。 第三半导体芯片附着到堆叠的第二半导体芯片的最上面，并且第三半导体芯片具有与连接到第二贯通电极的第一贯通电极和再分配线电连接的第二贯通电极。 外部连接端子附接到第三半导体芯片的再分配线路。 第二半导体芯片和第三半导体芯片堆叠的晶片级的第一半导体芯片在芯片级被锯切以用于半导体封装。

公开(公告)号：US20090189267A1

公开(公告)日：2009-07-30

申请号：US12059308

申请日：2008-03-31

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

IPC分类号： H01L23/02 ,  H01L23/52

CPC分类号： H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/13099

摘要： A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

摘要翻译： 具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。 芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。 可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。

公开(公告)号：US07898834B2

公开(公告)日：2011-03-01

申请号：US12059308

申请日：2008-03-31

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

IPC分类号： G11C5/02

CPC分类号： H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/13099

摘要： A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

摘要翻译： 具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。 芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。 可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。

公开(公告)号：US20090166853A1

公开(公告)日：2009-07-02

申请号：US12048304

申请日：2008-03-14

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

IPC分类号： H01L23/36

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.

摘要翻译： 堆叠的晶片级半导体封装模块包括半导体芯片模块，其包括具有矩形形状的第一和第二半导体芯片。 第一半导体芯片具有沿其下表面的第一短边设置的第一焊盘。 第二半导体芯片具有沿其下表面的第一短边设置的第二焊盘。 第一和第二半导体芯片被堆叠以便在叠置的第一和第二半导体芯片的一侧上露出第一焊盘和第二焊盘。 封装还包括具有面向第一焊盘的第一连接焊盘和面向第二焊盘的第二连接焊盘的衬底。 该包装还包括用于将第一垫连接到第一连接垫的第一连接构件和用于将第二垫连接到第二连接垫的第二连接构件。

公开(公告)号：US08338921B2

公开(公告)日：2012-12-25

申请号：US13289365

申请日：2011-11-04

申请人： Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee ,  Tac Keun Oh ,  Sang Joon Lim

发明人： Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee ,  Tac Keun Oh ,  Sang Joon Lim

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

摘要翻译： 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US07859102B2

公开(公告)日：2010-12-28

申请号：US12048304

申请日：2008-03-14

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

IPC分类号： H01L23/36

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.

摘要翻译： 堆叠的晶片级半导体封装模块包括半导体芯片模块，其包括具有矩形形状的第一和第二半导体芯片。 第一半导体芯片具有沿其下表面的第一短边设置的第一焊盘。 第二半导体芯片具有沿其下表面的第一短边设置的第二焊盘。 第一和第二半导体芯片被堆叠以便在叠置的第一和第二半导体芯片的一侧上露出第一焊盘和第二焊盘。 封装还包括具有面向第一焊盘的第一连接焊盘和面向第二焊盘的第二连接焊盘的衬底。 该包装还包括用于将第一垫连接到第一连接垫的第一连接构件和用于将第二垫连接到第二连接垫的第二连接构件。

公开(公告)号：US08202762B2

公开(公告)日：2012-06-19

申请号：US13218916

申请日：2011-08-26

申请人： Sung Min Kim ,  Min Suk Suh

发明人： Sung Min Kim ,  Min Suk Suh

IPC分类号： H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2224/05099

摘要： A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

摘要翻译： 堆叠封装包括上半导体芯片，其具有形成在上半导体芯片的上表面上的多个第一焊盘和在相应的第一焊盘下方的上半导体芯片中限定的通孔; 以及下半导体芯片，其安装在上半导体芯片的下表面，并且具有多个第二焊盘，其形成在下半导体芯片的上表面上，并且形成在各个第二焊盘上并被插入 各个通孔将进入相应的第一接合焊盘。