Patent search ap:("Jongho Lee") AND inv:"Jongho Lee" Page 2

11.

发明申请
Method for identifying and evaluating parallel motor control function in the brain based on electromyogram signals 失效
Title translation: 基于肌电信号识别和评估大脑平行电机控制功能的方法

公开(公告)号：US20110213267A1

公开(公告)日：2011-09-01

申请号：US12807861

申请日：2010-09-15

Applicant: Shinji Kakei , Jongho Lee , Yasuhiro Kagamihara

Inventor： Shinji Kakei , Jongho Lee , Yasuhiro Kagamihara

IPC: A61B5/0488

CPC classification number: A61B5/4528 , A61B5/0488 , A61B5/11 , A61B5/1121 , A61B5/4064 , A61B5/6824

Abstract: The present invention provides a system for evaluating motor control function in the brain. This system is for evaluating the motor control function in the brain of a subject from the electromyogram (EMG) data of joint prime movers and the data on the position, velocity and acceleration of the joint, wherein both of the data have been obtained by measuring a target-tracking movement performed by the subject with a motion measurement unit that tracks a moving target, the system comprising the following means (a) to (c): (a) means for separating the frequencies of the EMG data and the frequencies of the data on the position, velocity and acceleration into a plurality of frequency components; (b) means for determining the ratio of viscosity coefficient to elastic coefficient (B/K ratio) for each of the frequency components by applying the EMG data and the data on the position, velocity and acceleration to a specific movement equation; and (c) means for evaluating the causal relationship between the motor control function in the brain and the target-tacking movement using the B/K ratio as an index.

Abstract translation: 本发明提供一种用于评估大脑中的运动控制功能的系统。该系统用于从关节原动机的肌电图（EMG）数据和关节的位置，速度和加速度数据中评估受试者的脑中的运动控制功能，其中两个数据都是通过测量获得的由跟踪移动目标的运动测量单元由对象执行的目标跟踪运动，该系统包括以下装置（a）至（c）：（a）用于将EMG数据的频率和频率分离的装置关于位置，速度和加速度进入多个频率分量的数据; （b）通过将EMG数据和关于位置，速度和加速度的数据应用于特定运动方程来确定每个频率分量的粘度系数与弹性系数（B / K比）的比率的装置; 和（c）使用B / K比作为指标来评估大脑中的运动控制功能与目标定位运动之间的因果关系的装置。

12.

发明申请
Liquid Filtration Using Pressure Difference Across a Hydrophobic Membrane 有权
Title translation: 通过疏水膜的压力差进行液体过滤

公开(公告)号：US20100176057A1

公开(公告)日：2010-07-15

申请号：US12685315

申请日：2010-01-11

Applicant: Rohit N. Karnik , Jongho Lee

Inventor： Rohit N. Karnik , Jongho Lee

IPC: B01D61/36 , B01D69/10 , B01D69/12

CPC classification number: B01D61/364 , B01D65/102 , B01D2325/08 , B01D2325/38 , C02F1/44 , C02F1/441 , C02F1/444 , C02F1/445 , C02F1/448 , C02F2103/08 , Y02A20/131

Abstract: Method and devices for filtering liquid are provided that rely on pressure difference to filter liquid. In one embodiment, a device for filtering liquid includes a feed chamber, a permeate chamber, and a porous membrane that is at least partially hydrophobic and has one or more pores configured to be permeable to vapor. A pressure of a liquid substance in the feed chamber is increased such that vapor of the liquid substance is transported from the feed chamber to the permeate chamber. The resistance of flow in a hydrophilic layer of the membrane can be controlled to make the membrane defect-tolerant. In another embodiment, a second porous membrane is further included and the second porous membrane is spaced apart from the first porous membrane. Various methods for filtering liquid are also provided.

Abstract translation: 提供过滤液体的方法和装置，其依赖于压力差来过滤液体。在一个实施例中，用于过滤液体的装置包括进料室，渗透室和至少部分疏水并且具有构造成可透过蒸汽的一个或多个孔的多孔膜。进料室中的液体物质的压力增加，使得液体物质的蒸汽从进料室输送到渗透室。可以控制膜的亲水层中的流动阻力以使膜具有缺陷。在另一个实施方案中，还包括第二多孔膜，并且第二多孔膜与第一多孔膜间隔开。还提供了用于过滤液体的各种方法。

13.

发明授权
Method for manufacturing homogeneous green bodies from the powders of multimodal particle size distribution using centrifugal casting 失效
Title translation: 使用离心铸造从多峰粒度分布的粉末制造均质生坯的方法

公开(公告)号：US06913716B2

公开(公告)日：2005-07-05

申请号：US10213454

申请日：2002-08-05

Applicant: Hae-Weon Lee , Huesup Song , Jongho Lee , Joosun Kim , Hyunick Shin

Inventor： Hae-Weon Lee , Huesup Song , Jongho Lee , Joosun Kim , Hyunick Shin

IPC: C04B35/622 , C04B35/573 , C04B35/634 , B29B9/08 , B29C35/02 , B29C39/02

CPC classification number: C04B35/634 , C04B35/573 , C04B35/6264 , C04B35/62655 , C04B35/62695 , C04B35/638 , C04B2235/3217 , C04B2235/3826 , C04B2235/48 , C04B2235/5436 , C04B2235/5445 , C04B2235/602 , C04B2235/94

Abstract: Disclosed is a method for manufacturing composite granules having a homogeneous particle distribution, comprising powders of multimodal particle size distribution and phenol resins, and a method for manufacturing green bodies having homogeneous microstructure without particle separation from the granules.

Abstract translation: 公开了一种制造具有均匀粒子分布的复合颗粒的方法，包括多峰粒度分布的粉末和酚醛树脂，以及一种制造具有均匀微观结构但不与颗粒分离的生坯体的方法。

14.

发明授权
Semiconductor package devices 有权
Title translation: 半导体封装器件

公开(公告)号：US09343437B2

公开(公告)日：2016-05-17

申请号：US14680094

申请日：2015-04-07

Applicant: Ae-nee Jang , Jin-Woo Park , Seokhyun Lee , Jongho Lee

Inventor： Ae-nee Jang , Jin-Woo Park , Seokhyun Lee , Jongho Lee

IPC: H01L23/10 , H01L25/065 , H01L23/373 , H01L23/367 , H01L23/528 , H01L23/31

CPC classification number: H01L25/0657 , H01L23/3107 , H01L23/3128 , H01L23/36 , H01L23/3675 , H01L23/3735 , H01L23/3736 , H01L23/42 , H01L23/49816 , H01L23/528 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06575 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2225/1094 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/00014 , H01L2924/00012 , H01L2924/00

Abstract: Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package.

Abstract translation: 提供半导体封装器件和形成半导体封装器件的方法。半导体封装器件可以包括下封装，其包括在下基板上的下半导体芯片，在上基板上包括上半导体芯片的上封装。上基板可以包括对应于下半导体芯片的突出部分和具有低于突出部分的底表面的底表面并且布置在突出部分周围的连接部分。半导体封装器件还可以包括在下半导体芯片和上基板上的突出部分之间的空间中的散热部分和将下封装电连接到上封装的封装连接图案。

15.

发明授权
Semiconductor devices and methods for fabricating the same 有权
Title translation: 半导体器件及其制造方法

公开(公告)号：US08482077B2

公开(公告)日：2013-07-09

申请号：US13102860

申请日：2011-05-06

Applicant: Jongho Lee , Chang-Bong Oh , Ho Lee , Myungsun Kim

Inventor： Jongho Lee , Chang-Bong Oh , Ho Lee , Myungsun Kim

IPC: H01L29/78

CPC classification number: H01L21/823807 , H01L21/28238 , H01L21/823412 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517

Abstract: A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道，第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

16.

发明申请
APPARATUS AND METHOD FOR MANUFACTURING VEHICLE DOOR TRIM AND VEHICLE DOOR TRIM MANUFACTURED USING THE METHOD 有权
Title translation: 使用该方法制造车辆门和车门的装置和方法

公开(公告)号：US20110311668A1

公开(公告)日：2011-12-22

申请号：US13221639

申请日：2011-08-30

Applicant: Jongho Lee

Inventor： Jongho Lee

IPC: B29C45/14

CPC classification number: B29C45/1635 , B29C45/27 , B29L2031/3005 , B60R13/0243

Abstract: A first mold has a core passage, and first and second cavities in fluid communication with each other at the core passage. A second mold has first and second nozzles therein that inject first and second resins to the first and second cavities, respectively. The core member is slidable within the core passage to provide or block the fluid communication between the cavities, and has a third nozzle therein to inject a third resin to the core passage. The first and second resins are injected into the cavities. The core member is moved to block the fluid communication between the cavities, before injecting the first and second resins is completed. The third resin is injected while moving the core member to provide the fluid communication, after injecting the first and second resins is completed. The molds are separated, thereby yielding a single molded product, such as a vehicle door trim.

Abstract translation: 第一模具具有芯通道，并且在芯通道处彼此流体连通的第一和第二空腔。第二模具在其中具有分别将第一和第二树脂注入到第一和第二空腔中的第一和第二喷嘴。芯构件可在芯通道内滑动以提供或阻挡空腔之间的流体连通，并且其中具有第三喷嘴以将第三树脂注入到芯通道。将第一和第二树脂注入到空腔中。在完成注入第一和第二树脂之前，移动芯构件以阻止空腔之间的流体连通。在移动芯部件以提供流体连通时注入第三树脂，在完成注入第一和第二树脂之后。模具被分离，从而产生单个模制产品，例如车门装饰件。

17.

发明申请
Dielectric layer for semiconductor device and method of manufacturing the same 有权

公开(公告)号：US20050074982A1

公开(公告)日：2005-04-07

申请号：US10999608

申请日：2004-11-29

Applicant: Jongho Lee , Nae-In Lee

Inventor： Jongho Lee , Nae-In Lee

IPC: H01L21/8247 , H01L21/02 , H01L21/28 , H01L21/31 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/94 , H01L21/00

CPC classification number: H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7881 , H01L29/94

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.

18.

发明申请
Semiconductor Package Devices 有权
Title translation: 半导体封装器件

公开(公告)号：US20150318266A1

公开(公告)日：2015-11-05

申请号：US14680094

申请日：2015-04-07

Applicant: Ae-nee Jang , Jin-Woo Park , Seokhyun Lee , Jongho Lee

Inventor： Ae-nee Jang , Jin-Woo Park , Seokhyun Lee , Jongho Lee

IPC: H01L25/065 , H01L23/31 , H01L23/528 , H01L23/373 , H01L23/367

CPC classification number: H01L25/0657 , H01L23/3107 , H01L23/3128 , H01L23/36 , H01L23/3675 , H01L23/3735 , H01L23/3736 , H01L23/42 , H01L23/49816 , H01L23/528 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06575 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2225/1094 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/00014 , H01L2924/00012 , H01L2924/00

Abstract: Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package.

Abstract translation: 提供半导体封装器件和形成半导体封装器件的方法。半导体封装器件可以包括下封装，其包括在下基板上的下半导体芯片，在上基板上包括上半导体芯片的上封装。上基板可以包括对应于下半导体芯片的突出部分和具有低于突出部分的底表面的底表面并且布置在突出部分周围的连接部分。半导体封装器件还可以包括在下半导体芯片和上基板上的突出部分之间的空间中的散热部分和将下封装电连接到上封装的封装连接图案。

19.

发明授权
Quantitative motor function evaluation system 有权
Title translation: 定量运动功能评估系统

公开(公告)号：US08792977B2

公开(公告)日：2014-07-29

申请号：US12674709

申请日：2008-02-26

Applicant: Shinji Kakei , Jongho Lee , Yasuhiro Kagamihara

Inventor： Shinji Kakei , Jongho Lee , Yasuhiro Kagamihara

IPC: A61B5/0488 , A61B5/00 , A61B5/11

CPC classification number: A61B5/0488 , A61B5/1124 , A61B5/4076 , A61B5/4082 , A61B5/4088 , A61B5/4528

Abstract: The system of the present invention includes (a) means for displaying image information including a target image and a cursor image for tracking the target image; (b) means used when the subject moves the cursor image; (c) means for detecting the state of tracking the target image by the cursor image; (d) means for detecting the muscle active state of the subject using the means (b); (e) means for analyzing the tracking state detected by the means (c) and the muscle active state detected by the means (d); and (f) means for evaluating the motor function of the subject by using results of analysis obtained by the means (e) as indexes.

Abstract translation: 本发明的系统包括：（a）用于显示包括目标图像和用于跟踪目标图像的光标图像的图像信息的装置; （b）当被摄体移动光标图像时使用的装置; （c）用于通过光标图像检测跟踪目标图像的状态的装置; （d）使用装置（b）检测受试者的肌肉活动状态的装置; （e）用于分析由装置（c）检测到的跟踪状态和由装置（d）检测到的肌肉活动状态的装置; 和（f）通过使用方法（e）作为指标获得的分析结果来评价受试者的运动功能的装置。