利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

31 条记录 (耗时 0.023 秒)

    Method of forming self-limiting polysilicon LOCOS for DRAM cell
    12.
    发明授权
    Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
    DRAM单元形成自限多晶硅LOCOS的方法

    公开(公告)号：US06309924B1

    公开(公告)日：2001-10-30

    申请号：US09585898

    申请日：2000-06-02

    申请人： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    发明人： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/10861 ,  H01L27/10867

    摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

    摘要翻译： 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。 然后将一层非晶硅沉积在氮化物衬垫上。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

    FORMING FACET-LESS EPITAXY WITH A CUT MASK
    13.
    发明申请
    FORMING FACET-LESS EPITAXY WITH A CUT MASK 有权
    用切割面膜形成面积小的外观

    公开(公告)号：US20130313647A1

    公开(公告)日：2013-11-28

    申请号：US13478411

    申请日：2012-05-23

    申请人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/8234 ,  H01L27/088

    CPC分类号： H01L21/823807 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

    摘要： A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

    摘要翻译： 提供了在基板上形成半导体结构的方法。 该方法可以包括在衬底的区域上制备连续的有源层并且在连续有源层的第一区域上沉积第一凸起的外延层。 第二凸起外延层也沉积在连续有源层的第二区上，使得第一凸起外延层紧邻第二凸起外延层。 可以使用掩模将沟槽结构蚀刻到第一和第二凸起外延层两端的连续有源层，由此蚀刻沟槽结构填充有用于将第一凸起外延层与第二凸起外延层电隔离的隔离材料 。

    Forming facet-less epitaxy with a cut mask
    16.
    发明授权
    Forming facet-less epitaxy with a cut mask 有权
    用切割面罩形成小面外延

    公开(公告)号：US08658486B2

    公开(公告)日：2014-02-25

    申请号：US13478411

    申请日：2012-05-23

    申请人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

    摘要： A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

    摘要翻译： 提供了在基板上形成半导体结构的方法。 该方法可以包括在衬底的区域上制备连续的有源层并且在连续有源层的第一区域上沉积第一凸起的外延层。 第二凸起外延层也沉积在连续有源层的第二区上，使得第一凸起外延层紧邻第二凸起外延层。 可以使用掩模将沟槽结构蚀刻到第一和第二凸起外延层两端的连续有源层，由此蚀刻沟槽结构填充有用于将第一凸起外延层与第二凸起外延层电隔离的隔离材料 。

    FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION
    17.
    发明申请
    FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION 有权
    具有自对准隔离的成形面较小的外观

    公开(公告)号：US20140027820A1

    公开(公告)日：2014-01-30

    申请号：US13556406

    申请日：2012-07-24

    申请人： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/76232 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.

    摘要翻译： 形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。 第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。 第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。 使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。 沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

    Digital interface for fast, inline, statistical characterization of process, MOS device and circuit variations
    18.
    发明授权
    Digital interface for fast, inline, statistical characterization of process, MOS device and circuit variations 有权
    数字接口，用于快速，在线，统计表征过程，MOS器件和电路变化

    公开(公告)号：US08587288B2

    公开(公告)日：2013-11-19

    申请号：US12823984

    申请日：2010-06-25

    申请人： Azeez Jennudin Bhavnagarwala ,  Stephen V. Kosonocky ,  Carl John Radens ,  Kevin Geoffrey Stawiasz

    发明人： Azeez Jennudin Bhavnagarwala ,  Stephen V. Kosonocky ,  Carl John Radens ,  Kevin Geoffrey Stawiasz

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/3004

    摘要： A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of

    摘要翻译： 提供了一种用于快速准确地统计表征CMOS工艺结构，MOS器件和电路参数的电气特性变化的电路架构和方法。 所提出的电路架构和方法使得在<2mV或<1nA分辨率的测试设备的电压或电流变化的分辨率精度下<1ms / DC扫描的统计特征吞吐量。 提出的电路架构的显着特征包括一个可激励被测器件的可编程斜坡电压发生器，一个双输入9-11位循环ADC，用于捕获输入和输出来自被测器件的直流电压/电流信号，一个2 Kb的锁存器 存储器，以可编程粒度的直流扫描为每个测量点捕获9-11位流，以及时钟和控制方案，其能够连续测量和流出数字数据块，从该模块重新测量被测器件的模拟特性 。