Abstract:
A wafer support structure for use in a chamber used for semiconductor fabrication of wafers is provided. The wafer support structure includes a dielectric block. A first electrode is embedded in a top half of the dielectric block. The first electrode is configured for connection to a direct current (DC) power source. A second electrode is embedded in a bottom half of the dielectric block. A vertical connection is embedded in the dielectric block for electrically coupling the second electrode to the first electrode.
Abstract:
An edge ring for use in a plasma processing chamber with a chuck is provided. An edge ring body has a first surface to be placed over and facing the chuck, wherein the first surface forms a ring around an aperture. A first elastomer ring is integrated to the first surface and extending around the aperture.
Abstract:
A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.
Abstract:
A method is provided and includes: determining a temperature distribution pattern across a substrate or a support plate of a substrate support; determining, based on the temperature distribution pattern, a number of masks to apply to a top surface of the support plate, where the number of masks is greater than or equal to two; and determining patterns of the masks based on the temperature distribution pattern; and applying the masks over the top surface. The method further includes: performing a first machining process to remove a portion of the support plate unprotected by the masks to form first mesas and first recessed areas between the first mesas; removing a first mask from the support plate; performing a second machining process to form second recessed areas and at least one of second mesas or a first seal band area; and removing a second mask from the support plate.
Abstract:
An exemplary method is directed to powering heaters in a substrate support assembly on which a semiconductor substrate is supported. The support assembly has an array of heaters powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to a power supply and at least two of the heaters and each power return line is connected to at least two of the heaters, and a switching device which independently connects each one of the heaters to one of the power supply lines and one of the power return lines so as to provide time-averaged power to each of the heaters by time divisional multiplexing of switches of the switching device. The method includes supplying power to each of the heaters sequentially using a time-domain multiplexing scheme.
Abstract:
An electrostatic chuck for a substrate processing system is provided. The electrostatic chuck includes: a top plate configured to electrostatically clamp to a substrate and formed of ceramic; an intermediate layer disposed below the top plate; and a baseplate disposed below the intermediate layer and formed of ceramic. The intermediate layer bonds the top plate to the baseplate.
Abstract:
A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness.
Abstract:
A substrate processing apparatus for processing substrates comprises a processing chamber in which a substrate is processed. A process gas source is adapted to supply process gas into the processing chamber. A RF energy source is adapted to energize the process gas into a plasma state in the processing chamber. A vacuum source is adapted to exhaust byproducts of the processing from the processing chamber. The processing chamber includes an electrostatic chuck assembly having a layer of ceramic material that includes an upper electrostatic clamping electrode and at least one RF electrode, a temperature controlled RF powered baseplate, and at least one annular electrically conductive gasket extending along an outer portion of an upper surface of the temperature controlled RF powered baseplate. The at least one annular electrically conductive gasket electrically couples the upper surface of the temperature controlled RF powered baseplate to the at least one RF electrode.
Abstract:
An edge ring is provided for use with an electrostatic wafer chuck and an electrostatic ring chuck with a central aperture with a cooling groove and with ring clamping electrodes and at least one ring backside temperature channel to regulate the temperature of the edge ring. The edge ring comprises an edge ring body to be placed over the electrostatic ring chuck with ring clamping electrodes, wherein the edge ring body comprises conductive portions which are placed over the ring clamping electrodes, when the edge ring body is placed over the electrostatic ring chuck and a first elastomer ring integrated to a first surface of the edge ring body and surrounding a central aperture of the first surface, wherein when the edge ring body is placed over the electrostatic ring chuck, the first elastomer ring is used to seal the cooling groove.
Abstract:
An Electrostatic Chuck (ESC) in a chamber of a semiconductor manufacturing apparatus is presented for eliminating cooling-gas light-up. One wafer support includes a baseplate connected to a radiofrequency power source, a dielectric block, gas supply channels for cooling the wafer bottom, and first and second electrodes. The dielectric block is situated above the baseplate and supports the wafer when present. The first electrode is embedded in the top half of the dielectric block, where the top surface of the first electrode is substantially parallel to a top surface of the dielectric block, and the first electrode is connected to a DC power source. Further, the second electrode is embedded in a bottom half of the dielectric block, the second electrode being electrically connected to the first electrode, where the bottom surface of the second electrode is substantially parallel to a top surface of the baseplate.