公开(公告)号：US20190067298A1

公开(公告)日：2019-02-28

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/08 ,  G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: H01L27/11273 ,  G11C5/063 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4085 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/10814 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1128 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/90 ,  H01L29/0847

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20180374855A1

公开(公告)日：2018-12-27

申请号：US15895928

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Chandra Mouli ,  Sanh D. Tang

IPC: H01L27/108 ,  H01L29/78

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

公开(公告)号：US09923029B2

公开(公告)日：2018-03-20

申请号：US15478100

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/24 ,  H01L27/102 ,  G11C13/00 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L21/768 ,  H01L23/528 ,  H01L24/80 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1608 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.

公开(公告)号：US20170271411A1

公开(公告)日：2017-09-21

申请号：US15478100

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/24 ,  G11C13/00 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L27/102 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L21/768 ,  H01L23/528 ,  H01L24/80 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1608 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.

公开(公告)号：US20170236589A1

公开(公告)日：2017-08-17

申请号：US15583411

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/161 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  G11C16/04 ,  H01L27/11582

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US20170117295A1

公开(公告)日：2017-04-27

申请号：US15398303

申请日：2017-01-04

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11597 ,  H01L29/24 ,  H01L27/1157 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US20160372556A1

公开(公告)日：2016-12-22

申请号：US15255402

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC: H01L29/40 ,  H01L27/115

CPC classification number: H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

公开(公告)号：US20160087071A1

公开(公告)日：2016-03-24

申请号：US14959884

申请日：2015-12-04

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L21/283

CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US20160087010A1

公开(公告)日：2016-03-24

申请号：US14865806

申请日：2015-09-25

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L21/768

CPC classification number: H01L27/2463 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L21/768 ,  H01L23/528 ,  H01L24/80 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1608 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.

Abstract translation: 一些实施例包括存储器单元的垂直堆叠，其中各个存储器单元各自具有存储元件，字线，位线和至少一个二极管。 存储器单元可以对应于交叉点存储器，并且二极管可以对应于包含夹在金属层之间的两个或多个电介质层的带隙工程二极管。 介电材料的隧道性质和金属的载流子注入性能可以被调整为将所需的性质设计到二极管中。 二极管可以位于位线和存储器元件之间，或者可以放置在字线和存储元件之间。 一些实施例包括形成交叉点存储器阵列的方法。 存储器阵列可以包含存储单元单元的垂直堆叠，其中单个单元单元包含交叉点存储器和至少一个二极管。

公开(公告)号：US20140339572A1

公开(公告)日：2014-11-20

申请号：US14447884

申请日：2014-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chandra Mouli

IPC: H01L27/115 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/11551 ,  H01L21/02529 ,  H01L21/3148 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell includes a channel region comprising silicon and carbon, a control gate, and a dielectric stack between the channel region and the control gate. A carbon content of the channel region of the second memory cell is less than a carbon content of the channel region of the first memory cell.

Abstract translation: 存储器包括形成在第一存储单元上的第一存储单元和第二存储单元。 第一存储单元和第二存储单元中的每一个包括在沟道区和控制栅之间包括硅和碳的沟道区，控制栅和电介质叠层。 第二存储单元的沟道区的碳含量小于第一存储单元的沟道区的碳含量。