公开(公告)号：US09705078B2

公开(公告)日：2017-07-11

申请号：US14981198

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  John K. Zahurak

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L45/1266 ,  H01L21/28114 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66621 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1691

Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US09595664B2

公开(公告)日：2017-03-14

申请号：US14595955

申请日：2015-01-13

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: H01L43/12 ,  G11C11/16 ,  H01L29/66

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/66007 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract translation: 提供包括非磁性桥的磁性单元结构以及制造该结构的方法。 磁性电池结构包括自由层，钉扎层和电连接自由层和钉扎层的非磁性桥。 非磁性桥的形状和/或构造使编程电流通过磁性单元结构，使得结构自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

公开(公告)号：US09437442B2

公开(公告)日：2016-09-06

申请号：US13924790

申请日：2013-06-24

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Jun Liu

IPC: H01L21/306 ,  C09G1/02 ,  C09K3/14

CPC classification number: H01L21/30625 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463

Abstract: A slurry for polishing a phase change material, such as Ge—Sb—Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at least one of damage to (e.g., scratching of) a polished surface of phase change material, an amount of force to be applied during polishing, and a static etch rate of the phase change material, while optionally providing selectivity for the phase change material over adjacent dielectric materials. A polishing method includes applying a slurry with one or more of the above-noted properties to a phase change material, as well as bringing the polishing pad into frictional contact with the phase change material. Polishing systems are disclosed that include a plurality of sources of solids (e.g., abrasive particles) and provide for selectivity in the solids that are applied to a substrate or polishing pad.

Abstract translation: 用于抛光相变材料（例如Ge-Sb-Te或锗 - 锑 - 碲（GST））的浆料包括尺寸小的磨料颗粒，其至少使得抛光表面的（例如，划伤） 相变材料，在抛光期间施加的力的量和相变材料的静态蚀刻速率，同时可选地为相变材料在相邻介电材料上提供选择性。 抛光方法包括将具有上述性质的一种或多种的浆料施加到相变材料上，以及使抛光垫与相变材料摩擦接触。 公开了抛光系统，其包括多个固体源（例如，磨料颗粒），并提供施加到基底或抛光垫的固体中的选择性。

公开(公告)号：US09373392B2

公开(公告)日：2016-06-21

申请号：US14599905

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: G11C13/00 ,  H01L27/102 ,  G11C5/02 ,  G11C5/06

CPC classification number: G11C13/0004 ,  C07D213/81 ,  C07D401/06 ,  C07D401/12 ,  C07D401/14 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/1021

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

公开(公告)号：US09361979B2

公开(公告)日：2016-06-07

申请号：US14702330

申请日：2015-05-01

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Jun Liu

IPC: G11C5/02 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

公开(公告)号：US20160118118A1

公开(公告)日：2016-04-28

申请号：US14982810

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/165

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

公开(公告)号：US20160078936A1

公开(公告)日：2016-03-17

申请号：US14940386

申请日：2015-11-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4097 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

公开(公告)号：US09218863B2

公开(公告)日：2015-12-22

申请号：US13673130

申请日：2012-11-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Steve Kramer ,  Gurtej Sandhu

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

CPC classification number: G11C11/161 ,  G11C11/16 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.

Abstract translation: 提供了包括压电材料的磁存储单元和操作存储单元的方法。 存储单元包括堆叠，并且压电材料可以形成为堆叠中的层或邻近电池堆的层。 压电材料可以用于在编程存储器单元期间引起瞬态应力以减小存储器单元的关键开关电流。

公开(公告)号：US09190265B2

公开(公告)日：2015-11-17

申请号：US14247653

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L21/8239 ,  H01L21/02 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L21/02225 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract translation: 一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。 掺杂区域提供相反导电类型的结。 在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。 在移除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含该结作为pn结 。 存储器件包括绝缘体材料上的粘合材料并将字线连接到绝缘体材料上。

公开(公告)号：US09123415B2

公开(公告)日：2015-09-01

申请号：US14191586

申请日：2014-02-27

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L47/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

Abstract: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode.

Abstract translation: PCRAM电池具有更接近相变材料的较高电阻率的梯度或分层的电阻率底部电极，以在电池和底部电极之间的界面附近提供部分加热，防止非晶态GST区域与底部电极分离，并且减少 编程电流要求。 底部电极也可以是锥形的，以在底部电极的顶部具有比在底部电极的底部更小的横截面积。