公开(公告)号：US11775185B2

公开(公告)日：2023-10-03

申请号：US16948426

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Walter Di Francesco ,  Yuanhang Cao ,  Luca De Santis ,  Fumin Gu

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5018

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

公开(公告)号：US20230266890A1

公开(公告)日：2023-08-24

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/28 ,  G06F1/08

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US10854305B2

公开(公告)日：2020-12-01

申请号：US16820636

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C16/04 ,  G11C29/50 ,  G11C29/52 ,  G06F12/02

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

公开(公告)号：US10593412B2

公开(公告)日：2020-03-17

申请号：US16040382

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C29/50 ,  G11C16/04 ,  G11C29/52 ,  G06F12/02

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.

公开(公告)号：US12189949B2

公开(公告)日：2025-01-07

申请号：US18049121

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Tommaso Vali ,  Walter Di Francesco ,  Luigi Pilolli ,  Angelo Covello ,  Andrea D'Alessandro ,  Agostino Macerola ,  Cristina Lattaro ,  Claudia Ciaschi

IPC: G06F3/06

Abstract: In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.

公开(公告)号：US20250006292A1

公开(公告)日：2025-01-02

申请号：US18440619

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Taylor Alu ,  Nicola Ciocchini ,  Shyam Sunder Raghunathan ,  Guang Hu ,  Walter Di Francesco ,  Umberto Siciliani ,  Violante Moschiano ,  Karan Banerjee

IPC: G11C29/52 ,  G11C16/20 ,  G11C16/34

Abstract: A method includes detecting a change in a memory control signal of a memory device including memory blocks, determining based at least on the change in the memory control signal that the memory device is in a stable state, and responsive to determining that the memory device is in the stable state, associating a voltage offset bin with at least one memory block of the memory device.

公开(公告)号：US12183407B2

公开(公告)日：2024-12-31

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

公开(公告)号：US20240428872A1

公开(公告)日：2024-12-26

申请号：US18800552

申请日：2024-08-12

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

公开(公告)号：US20240427507A1

公开(公告)日：2024-12-26

申请号：US18827515

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/28

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20240203501A1

公开(公告)日：2024-06-20

申请号：US18404282

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Walter Di Francesco ,  Violante Moschiano ,  Umberto Siciliani

IPC: G11C16/10 ,  G06F12/0802 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F12/0802 ,  G11C16/0483 ,  G06F2212/60 ,  G06F2212/72 ,  G11C11/56

Abstract: Control logic in a memory device initiates a programming operation to program a set of memory cells of the memory device to a target programming level of a set of programming levels. During execution of the programming operation, a programming status associated with the set of memory cells. In response to determining the programming status satisfies a condition, causing a release of a set of data associated with the programming operation from a cache register.