公开(公告)号：US10090317B2

公开(公告)日：2018-10-02

申请号：US15221131

申请日：2016-07-27

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L21/3205 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04 ,  H01L27/1157

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US10079246B2

公开(公告)日：2018-09-18

申请号：US15849242

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L21/336 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11524 ,  H01L21/02 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20180138196A1

公开(公告)日：2018-05-17

申请号：US15849242

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11524 ,  H01L21/02 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US09853046B2

公开(公告)日：2017-12-26

申请号：US15174478

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L29/76 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/02 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US09437442B2

公开(公告)日：2016-09-06

申请号：US13924790

申请日：2013-06-24

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Jun Liu

IPC: H01L21/306 ,  C09G1/02 ,  C09K3/14

CPC classification number: H01L21/30625 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463

Abstract: A slurry for polishing a phase change material, such as Ge—Sb—Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at least one of damage to (e.g., scratching of) a polished surface of phase change material, an amount of force to be applied during polishing, and a static etch rate of the phase change material, while optionally providing selectivity for the phase change material over adjacent dielectric materials. A polishing method includes applying a slurry with one or more of the above-noted properties to a phase change material, as well as bringing the polishing pad into frictional contact with the phase change material. Polishing systems are disclosed that include a plurality of sources of solids (e.g., abrasive particles) and provide for selectivity in the solids that are applied to a substrate or polishing pad.

Abstract translation: 用于抛光相变材料（例如Ge-Sb-Te或锗 - 锑 - 碲（GST））的浆料包括尺寸小的磨料颗粒，其至少使得抛光表面的（例如，划伤） 相变材料，在抛光期间施加的力的量和相变材料的静态蚀刻速率，同时可选地为相变材料在相邻介电材料上提供选择性。 抛光方法包括将具有上述性质的一种或多种的浆料施加到相变材料上，以及使抛光垫与相变材料摩擦接触。 公开了抛光系统，其包括多个固体源（例如，磨料颗粒），并提供施加到基底或抛光垫的固体中的选择性。

公开(公告)号：US20150123188A1

公开(公告)日：2015-05-07

申请号：US14069553

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun J. Hu ,  Haitao Liu

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

Abstract translation: 公开了形成一串存储器单元的方法，具有一串存储单元的装置和系统。 一种用于形成存储单元串的方法包括在衬底上形成金属硅化物源材料。 掺杂金属硅化物源材料。 在金属硅化物源材料上形成垂直的存储单元串。 半导体材料垂直地形成并且与垂直的存储单元串相邻并且耦合到金属硅化物源材料。

公开(公告)号：US08940592B2

公开(公告)日：2015-01-27

申请号：US13739679

申请日：2013-01-11

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Haitao Liu ,  Zhenyu Lu

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01J37/32

CPC classification number: H01L27/1222 ,  H01J37/32412 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02595 ,  H01L21/2236 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/324 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66757

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract translation: 公开了形成薄膜晶体管和存储器的方法。 在一种这样的方法中，多晶硅是掺杂氢的等离子体以形成掺杂的多晶硅。 然后将掺杂的多晶硅退火。 氢等离子体掺杂和退火是去耦合的。

公开(公告)号：US10340287B2

公开(公告)日：2019-07-02

申请号：US16111762

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: G11C16/04 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/02 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US10038002B2

公开(公告)日：2018-07-31

申请号：US15296858

申请日：2016-10-18

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L21/285 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/66825

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20160336341A1

公开(公告)日：2016-11-17

申请号：US15221131

申请日：2016-07-27

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.