公开(公告)号：US20210166996A1

公开(公告)日：2021-06-03

申请号：US17175006

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

公开(公告)号：US10777523B2

公开(公告)日：2020-09-15

申请号：US16387771

申请日：2019-04-18

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US10438928B2

公开(公告)日：2019-10-08

申请号：US14626575

申请日：2015-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

公开(公告)号：US20170358547A1

公开(公告)日：2017-12-14

申请号：US15687691

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/13 ,  H01L22/14 ,  H01L22/20 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02215 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03914 ,  H01L2224/03916 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05565 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/11632 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0474 ,  H01L2924/0503 ,  H01L2924/05994 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/05432

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US09780052B2

公开(公告)日：2017-10-03

申请号：US14853807

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/00 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02135 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/114 ,  H01L2224/11472 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053

Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

公开(公告)号：US11430809B2

公开(公告)日：2022-08-30

申请号：US16984457

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H01L27/11582 ,  G11C5/02 ,  H01L21/768 ,  G11C16/04 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11233036B2

公开(公告)日：2022-01-25

申请号：US17183276

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L21/50 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

公开(公告)号：US20220013534A1

公开(公告)日：2022-01-13

申请号：US16922792

申请日：2020-07-07

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.

公开(公告)号：US11222825B2

公开(公告)日：2022-01-11

申请号：US16814750

申请日：2020-03-10

Applicant: Micron Technology, Inc.

Inventor： Corey Staller ,  Anilkumar Chandolu

IPC: H01L21/8234 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.

公开(公告)号：US20210327885A1

公开(公告)日：2021-10-21

申请号：US16851638

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. McKinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11578

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.