公开(公告)号：US09490226B2

公开(公告)日：2016-11-08

申请号：US14462265

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/34 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H05K1/0207 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract translation: 本文提供了一种集成器件，其包括衬底，管芯，位于衬底和管芯之间的散热层和被配置为将管芯耦合到散热层的第一互连。 散热层可以被配置成为接地信号提供电路径。 第一互连可以被进一步配置成将热量从管芯传导到散热层。 集成器件还可以包括配置成将管芯耦合到衬底的第二互连。 第二互连可以被进一步配置为在管芯和衬底之间传导功率信号。 集成器件还可以包括位于散热层和衬底之间的介电层，以及位于管芯和散热层之间的阻焊层。

公开(公告)号：US09335384B2

公开(公告)日：2016-05-10

申请号：US14037142

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: G01R33/02 ,  G01R29/08

CPC classification number: G01R33/02 ,  G01R29/0814

Abstract: A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.

Abstract translation: 一种用于测试电子设备的近场磁场的方法和装置。 该方法包括使用在第一方向上定向的环形天线来测量磁场。 在测量磁场的同时，将环形天线扫过所需的方位角范围。 一旦第一方向测试完成，环形天线就变成第二定位方向。 然后在第二取向方向上测量磁场，并且扫过第二方向上所需的取向角范围。 该装置提供连接到同轴探针的环形天线，同轴电缆用作中心导体和两个外部导体。 轴安装在环形天线上，并连接到步进电机。 还提供用于移动臂组件的伺服电动机。

公开(公告)号：US20160013125A1

公开(公告)日：2016-01-14

申请号：US14329646

申请日：2014-07-11

Applicant: QUALCOMM INCORPORATED

Inventor： Dong Wook Kim ,  Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L23/498 ,  H05K3/28 ,  H05K3/46 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K3/284 ,  H05K3/46 ,  H05K2203/1316

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

Abstract translation: 一些新颖的特征涉及包括衬底，耦合到衬底的第一互连和围绕第一互连的第二互连的集成器件。 第二互连可以被配置为提供到地的电连接。 在一些实现中，第二互连包括板。 在一些实施方案中，集成器件还包括在第一互连和第二互连之间的介电材料。 在一些实施方案中，集成装置还包括围绕第二互连的模具。 在一些实现中，第一互连被配置为在第一方向上传导功率信号。 在一些实现中，第二互连被配置为在第二方向上传导接地信号。 在一些实施方式中，第二方向与第一方向不同。 在一些实施方式中，集成器件可以是封装封装（PoP）器件。

公开(公告)号：US20150311275A1

公开(公告)日：2015-10-29

申请号：US14791164

申请日：2015-07-02

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L49/02 ,  H01L23/498 ,  H01G4/012 ,  H01G4/30 ,  H01G4/12 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/306 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L27/0805 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16267 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/014

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

公开(公告)号：US09151779B2

公开(公告)日：2015-10-06

申请号：US13675673

申请日：2012-11-13

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K Song ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: G01R31/00 ,  G01R1/07

CPC classification number: G01R1/07 ,  G01R31/002

Abstract: Systems and methods for EMC, EMI and ESD testing are described. A probe comprises a center conductor extending along an axis of the probe, a probe tip, and a shield coaxially aligned with the center conductor and configured to provide electromagnetic screening for the probe tip. One or more actuators may change the relative positions of the probe tip and shield with respect to a device under test, thereby enabling control of sensitivity and resolution of the probe.

Abstract translation: 描述了用于EMC，EMI和ESD测试的系统和方法。 探针包括沿着探针的轴线延伸的中心导体，探针尖端和与中心导体同轴对准的屏蔽并且被配置为为探针尖端提供电磁屏蔽。 一个或多个致动器可以相对于被测器件改变探头尖端和屏蔽件的相对位置，从而能够控制探头的灵敏度和分辨率。

公开(公告)号：US20150084653A1

公开(公告)日：2015-03-26

申请号：US14038608

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: G01R27/02 ,  G01R31/28

CPC classification number: G01R27/02

Abstract: A method and apparatus for testing integrated circuit resistors includes applying a variable source current to a resistive device under test (DUT), measuring the resistance of the resistive DUT as a function of the source current, and fitting the measured resistance to parameters of a polynomial parametric equation, wherein the parametric equation comprises a constant resistance at zero current bias plus a second order current coefficient of resistance multiplied by the square of the current.

Abstract translation: 用于测试集成电路电阻的方法和装置包括将可变源电流施加到被测电阻器件（DUT），测量作为源电流的函数的电阻DUT的电阻，并将测得的电阻拟合到多项式的参数 参数方程式，其中参数方程包括零电流偏置处的恒定电阻加上电阻乘以电流平方的二阶电流电流系数。

公开(公告)号：US08987872B2

公开(公告)日：2015-03-24

申请号：US13794487

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L23/552 ,  H01L21/82 ,  H01L25/065 ,  H05K9/00 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/82 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K9/0007 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

Abstract translation: 一个特征涉及包括衬底和耦合到衬底的电磁干扰（EMI）屏蔽）的多芯片封装。 至少一个集成电路耦合到衬底的第一表面。 EMI屏蔽包括被配置为将封装与射频辐射屏蔽的金属外壳，耦合到金属外壳的内表面的至少一部分的电介质层和多个信号线。 信号线耦合到电介质层，并通过电介质层与金属外壳电隔离。 至少一个其它集成电路耦合到EMI屏蔽的内表面，并且EMI屏蔽的内表面的至少一部分面向基板的第一表面。 信号线被配置为向第二电路部件提供电信号。

公开(公告)号：US10079097B2

公开(公告)日：2018-09-18

申请号：US14736219

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01G4/228 ,  H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G2/06 ,  H01G4/232

CPC classification number: H01G4/228 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

公开(公告)号：US09621281B2

公开(公告)日：2017-04-11

申请号：US14546924

申请日：2014-11-18

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang

IPC: H04B10/80 ,  H01L25/16 ,  H04B10/114

CPC classification number: H04B10/803 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B10/1143 ,  H01L2924/00

Abstract: Some novel features pertain to a device that includes a first integrated device package and a second integrated device package. The first integrated device package includes a first package substrate, a first integrated device, and a first configurable optical transmitter. The first configurable optical transmitter is configured to be in communication with the first integrated device. The first configurable optical transmitter is configured to transmit an optical beam at a configurable angle. The first configurable optical transmitter includes an optical beam source, an optical beam splitter, and a set of phase shifters coupled to the optical beam splitter. The set of phase shifters is configured to enable the angle at which the optical beam is transmitted. The second integrated device package includes a second package substrate, a second integrated device, and a first optical receiver configured to receive the optical beam from the first configurable optical transmitter.

公开(公告)号：US09613942B2

公开(公告)日：2017-04-04

申请号：US14733201

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/065 ,  H01L23/50 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.