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公开(公告)号：US10541693B2
公开(公告)日：2020-01-21
申请号：US16242475
申请日：2019-01-08
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/091 , H03K5/156 , H03L7/00 , G11C7/10 , G11C7/22 , H04L7/00 , H04L7/033 , H03L7/08 , H03L7/099 , G11C7/04
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US10404258B2
公开(公告)日：2019-09-03
申请号：US15796608
申请日：2017-10-27
Applicant: Rambus Inc.
Inventor： Marko Aleksić , Brian S. Leibowitz
Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
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公开(公告)号：US20190222217A1
公开(公告)日：2019-07-18
申请号：US16247894
申请日：2019-01-15
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
CPC classification number: H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
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公开(公告)号：US20180329859A1
公开(公告)日：2018-11-15
申请号：US15947701
申请日：2018-04-06
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
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15.发明申请公开(公告)号：US20180248718A1
公开(公告)日：2018-08-30
申请号：US15878149
申请日：2018-01-23
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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Patent Agency Ranking
公开(公告)号：US20180145693A1
公开(公告)日：2018-05-24
申请号：US15796608
申请日：2017-10-27
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L1/00 , H03K3/0315 , H03L7/083 , H03L7/24
Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
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公开(公告)号：US09748960B2
公开(公告)日：2017-08-29
申请号：US14456716
申请日：2014-08-11
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/091 , H03L7/099 , H03L7/00 , G11C7/10 , G11C7/22 , H04L7/033 , H03L7/08 , H04L7/00 , G11C7/04
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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18.发明申请公开(公告)号：US20170207790A1
公开(公告)日：2017-07-20
申请号：US15390350
申请日：2016-12-23
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L7/24 , H03K5/26 , H03K2005/00286 , H03L7/081 , H03L7/099 , H03L7/0995
Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
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公开(公告)号：US09569308B1
公开(公告)日：2017-02-14
申请号：US14328941
申请日：2014-07-11
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brian S. Leibowitz
CPC classification number: G06F11/1048 , G06F11/1044 , G06F11/1076 , H03M13/356 , H03M13/6502
Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.
Abstract translation: 存储器控制器可操作在误差检测/校正模式中，其中N个校正子值分别应用于数据量的N个数据字，但是单个奇偶校验位在数据量的所有N个数据字上被共享。
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公开(公告)号：US09563597B2
公开(公告)日：2017-02-07
申请号：US14386561
申请日：2012-12-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Brian S. Leibowitz , Wayne Frederick Ellis , Akash Bansal , John Welsford Brooks , Kishore Ven Kasamsetty
CPC classification number: G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。
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