公开(公告)号：US20180024880A1

公开(公告)日：2018-01-25

申请号：US15709769

申请日：2017-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Damian Yurzola ,  Eran Sharon ,  Idan Alrod ,  Michael Altshuler ,  Madhuri Kotagiri ,  Rajeev Nagabhirava

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

公开(公告)号：US20170185299A1

公开(公告)日：2017-06-29

申请号：US15459578

申请日：2017-03-15

Applicant: SanDisk Technologies LLC

Inventor： Kevin Michael Conley ,  Raul-Adrian Cernea ,  Eran Sharon ,  Idan Alrod

IPC: G06F3/06 ,  G11C16/08 ,  G11C29/52 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/3459 ,  G11C29/52

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

公开(公告)号：US10732847B2

公开(公告)日：2020-08-04

申请号：US16262125

申请日：2019-01-30

Applicant: SanDisk Technologies LLC

Inventor： Alexander Bazarsky ,  Grishma Shah ,  Idan Alrod ,  Eran Sharon

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/04

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

公开(公告)号：US10114549B2

公开(公告)日：2018-10-30

申请号：US15073373

申请日：2016-03-17

Applicant: Sandisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Ariel Navon

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C16/34

Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.

公开(公告)号：US20180287634A1

公开(公告)日：2018-10-04

申请号：US15475602

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/118 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1102 ,  H03M13/1125 ,  H03M13/116 ,  H03M13/3715 ,  H03M13/616 ,  H03M13/6516 ,  H03M13/6566

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10090044B2

公开(公告)日：2018-10-02

申请号：US15215862

申请日：2016-07-21

Applicant: SanDisk Technologies LLC

Inventor： Stella Achtenberg ,  Alon Eyal ,  Eran Sharon

IPC: G11C29/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G06F11/10 ,  G11C29/52

Abstract: A memory system can program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming are selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which include one or more of a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, are used to program the blocks selected for burst mode programming. In this regard, burst mode programming is performed more quickly than normal mode programming.

公开(公告)号：US10089177B2

公开(公告)日：2018-10-02

申请号：US15061246

申请日：2016-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alexander Bazarsky ,  Ran Zamir ,  Eran Sharon ,  Idan Alrod

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  H03M13/37 ,  G11C29/00 ,  H03M13/15 ,  H03M13/29 ,  G11C16/34 ,  G11C29/52 ,  G11C29/04

Abstract: An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

公开(公告)号：US10083069B2

公开(公告)日：2018-09-25

申请号：US13928774

申请日：2013-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seungjune Jeon ,  Idan Alrod ,  Eran Sharon ,  Dana Lee

IPC: G11C29/00 ,  G06F11/07 ,  G11C29/02 ,  G11C16/34

CPC classification number: G06F11/0751 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028

Abstract: A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.

公开(公告)号：US10002086B1

公开(公告)日：2018-06-19

申请号：US15385324

申请日：2016-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Stella Achtenberg ,  Eran Sharon ,  Ran Zamir ,  Amir Shaharabany

IPC: H03M13/00 ,  G06F13/16 ,  G06F13/40 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F3/06

Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

公开(公告)号：US20180025776A1

公开(公告)日：2018-01-25

申请号：US15215862

申请日：2016-07-21

Applicant: SanDisk Technologies LLC

Inventor： Stella Achtenberg ,  Alon Eyal ,  Eran Sharon

IPC: G11C11/56 ,  G11C29/52 ,  G06F11/10 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C11/5628 ,  G06F11/1072 ,  G11C7/1018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/32 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641

Abstract: Apparatus and method for performing burst mode programming in a memory system are disclosed. A memory system may program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming may be selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which may include a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, may be used to program the blocks selected for burst mode programming. In this regard, burst mode programming may be performed more quickly than normal mode programming.