公开(公告)号：US20170133064A1

公开(公告)日：2017-05-11

申请号：US15341707

申请日：2016-11-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei NAGATSUKA ,  Tomokazu YOKOI ,  Naoaki TSUTSUI ,  Kazuaki OHSHIMA ,  Tatsuya ONUKI

IPC: G11C7/06 ,  G11C7/10 ,  G11C8/10 ,  G11C7/12 ,  H01L27/115 ,  G11C5/06

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.

公开(公告)号：US20170077101A1

公开(公告)日：2017-03-16

申请号：US15359873

申请日：2016-11-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Kiyoshi KATO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA

IPC: H01L27/105 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US20160064383A1

公开(公告)日：2016-03-03

申请号：US14935607

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Hiroki INOUE ,  Takanori MATSUZAKI

IPC: H01L27/108

CPC classification number: H01L27/108 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.

Abstract translation: 具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入次数没有限制。 在半导体装置中，以矩阵形式设置有各自包括第一晶体管，第二晶体管和电容器的多个存储单元，以及用于将一个存储单元连接到另一个存储单元的源（或称为位线） 第一晶体管的漏极电极通过第二晶体管的源极或漏极电极彼此电连接。 因此，布线数量可以比第一晶体管的源极或漏极以及第二晶体管的源极或漏极连接到不同的布线的情况下的布线数量小。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20150340076A1

公开(公告)日：2015-11-26

申请号：US14718143

申请日：2015-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC: G11C11/24 ,  H01L27/12 ,  H01L29/786 ,  G11C5/14 ,  H01L29/24

CPC classification number: G11C11/24 ,  G11C11/5621 ,  G11C11/565 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869

Abstract: A highly reliable storage device with small data deterioration is provided. The storage device includes a first circuit, a second circuit, a third circuit, and a memory cell. The first circuit has a function of detecting power-on. The second circuit has a function of specifying the address of the memory cell. The third circuit has a function of refreshing the memory cell at the address specified by the second circuit after the first circuit detects power-on. The memory cell preferably includes an oxide semiconductor transistor.

Abstract translation: 提供了具有小数据恶化的高度可靠的存储设备。 存储装置包括第一电路，第二电路，第三电路和存储单元。 第一电路具有检测上电功能。 第二电路具有指定存储单元的地址的功能。 第三电路具有在第一电路检测到上电之后刷新由第二电路指定的地址处的存储单元的功能。 存储单元优选地包括氧化物半导体晶体管。

公开(公告)号：US20230246255A1

公开(公告)日：2023-08-03

申请号：US18127072

申请日：2023-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Akihiro KIMURA

IPC: H01M10/44 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  H02J7/00 ,  H02J50/40

CPC classification number: H01M10/44 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  H02J7/00 ,  H02J50/402

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US20220375938A1

公开(公告)日：2022-11-24

申请号：US17772423

申请日：2020-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshihiro KOMATSU ,  Yasumasa YAMANE ,  Shuhei NAGATSUKA ,  Takashi HAMADA ,  Hiroki KOMAGATA

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device in which variation of characteristics is small is provided. A second insulator, an oxide, a conductive layer, and an insulating layer are formed over a first insulator; a third insulator and fourth insulator are deposited to be in contact with the first insulator; a first opening reaching the oxide is formed in the conductive layer, the insulating layer, the third insulator, and the fourth insulator; a fifth insulator, a sixth insulator, and a conductor are formed in the first opening; a seventh insulator is deposited over the fourth insulator, the fifth insulator, and the sixth insulator; a mask is formed in a first region over the seventh insulator in a top view; oxygen is implanted into a second region not overlapping the first region in the top view; heat treatment is performed; a second opening reaching the fourth insulator is formed in the seventh insulator; and heat treatment is performed.

公开(公告)号：US20220367450A1

公开(公告)日：2022-11-17

申请号：US17771565

申请日：2020-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shuhei NAGATSUKA ,  Takuya KAWATA ,  Ryota HODO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/108 ,  H01L27/1156 ,  H01L29/786 ,  H01L29/792

Abstract: A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, a third insulator over the second insulator, a fourth insulator over the third insulator, and an opening region. The opening region includes the second insulator, the third insulator over the second insulator, and the fourth insulator over the third insulator. The third insulator includes an opening reaching the second insulator. The fourth insulator is in contact with a top surface of the second insulator inside the opening.

公开(公告)号：US20220036928A1

公开(公告)日：2022-02-03

申请号：US17505110

申请日：2021-10-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: G11C5/06 ,  G11C11/4074 ,  G11C11/4091 ,  H01L27/108 ,  H01L29/786 ,  G11C7/10

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US20210152025A1

公开(公告)日：2021-05-20

申请号：US17159214

申请日：2021-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Akihiro KIMURA

IPC: H02J50/40 ,  H02J50/10 ,  H02J50/27 ,  H01M10/44 ,  H04B1/3883 ,  H02J7/00

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US20180033807A1

公开(公告)日：2018-02-01

申请号：US15658513

申请日：2017-07-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei MATSUDA ,  Daigo ITO ,  Daisuke MATSUBAYASHI ,  Yasutaka SUZUKI ,  Etsuko KAMATA ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/105 ,  H01L29/423

CPC classification number: H01L27/1251 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.